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| author | Andrew Burgess <andrew.burgess@embecosm.com> | 2016-03-31 19:51:14 +0100 |
|---|---|---|
| committer | Andrew Burgess <andrew.burgess@embecosm.com> | 2016-04-19 22:50:33 +0100 |
| commit | c8f785f220bab3c17fc93445ac509495d00d5afe (patch) | |
| tree | 4b845f17e4171fcffd0fb568df639a56f397011f /opcodes/arc-nps400-tbl.h | |
| parent | ee2915c993e333c2a1c26499da1a918516d2f1cc (diff) | |
| download | gdb-c8f785f220bab3c17fc93445ac509495d00d5afe.zip gdb-c8f785f220bab3c17fc93445ac509495d00d5afe.tar.gz gdb-c8f785f220bab3c17fc93445ac509495d00d5afe.tar.bz2 | |
opcodes/arc: Add more nps instructions
Add dctcp, dcip, dcet, and dcacl instructions.
gas/ChangeLog:
* testsuite/gas/arc/nps400-4.d: New file.
* testsuite/gas/arc/nps400-4.s: New file.
* testsuite/gas/arc/nps400-5.d: New file.
* testsuite/gas/arc/nps400-5.s: New file.
include/ChangeLog:
* opcode/arc.h (insn_class_t): Add NET and ACL class.
opcodes/ChangeLog:
* arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
Diffstat (limited to 'opcodes/arc-nps400-tbl.h')
| -rw-r--r-- | opcodes/arc-nps400-tbl.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h index 832d2ff..ebafc15 100644 --- a/opcodes/arc-nps400-tbl.h +++ b/opcodes/arc-nps400-tbl.h @@ -124,6 +124,25 @@ /* crc32<.r> 0,limm,u6 00111 110 01 110100 R 111 uuuuuu 111110 */ { "crc32", 0x3e74703e, 0xffff703f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, LIMM, UIMM6_20 }, { C_NPS_R }}, +/**** Protocol Decoder Instructions ****/ + +/* dctcp b,c 00111bbb001011110bbbcccccc000000 */ +{ "dctcp", 0x382f0000, 0xf8ff803f, ARC_OPCODE_NPS400, NET, NONE, { RB, RC }, { 0 }}, + +/* dcip a,b,c 00111bbb001011110bbbccccccaaaaaa */ +{ "dcip", 0x38290000, 0xf8ff8000, ARC_OPCODE_NPS400, NET, NONE, { RA, RB, RC }, { 0 }}, + +/* dcet b,c 00111bbb001011110bbbcccccc000010 */ +{ "dcet", 0x382f0002, 0xf8ff803f, ARC_OPCODE_NPS400, NET, NONE, { RB, RC }, { 0 }}, + +/* dcet a,b,c 00111bbb001000000bbbccccccaaaaaa */ +{ "dcet", 0x38200000, 0xf8ff8000, ARC_OPCODE_NPS400, NET, NONE, { RA, RB, RC }, { 0 }}, + +/**** ACL Instructions ****/ + +/* dcacl<.f> a,b,c 00111bbb001001010bbbccccccaaaaaa */ +{ "dcacl", 0x38250000, 0xf8ff0000, ARC_OPCODE_NPS400, ACL, NONE, { RA, RB, RC }, { C_F }}, + /**** Pipeline Control Instructions ****/ /* schd<.rw|.rd> */ |