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authorAndrew Burgess <andrew.burgess@embecosm.com>2016-09-27 12:06:01 +0100
committerAndrew Burgess <andrew.burgess@embecosm.com>2016-11-04 22:46:51 +0000
commitb437d035ddf4e4c0c566c577ee059790ed28ad9b (patch)
tree54da51c86dd768e89abcbb808a9a9c614fe87a6f /opcodes/arc-nps400-tbl.h
parent848ac659685fba46ce8816400db705f60c8040f7 (diff)
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arc/nps400: Validate address type operands correctly
When we match against an address type operand within an instruction it is important that we match exactly the right address type operand early on, during the opcode selection phase. If we wait until the operand insertion phase to check that we have the correct address operand, then it is too late to select an alternative opcode. This becomes important only when we have multiple opcodes with the same mnemonic, and operand lists that differ only in the type of the address operands. This commit fixes this issue, and adds some example instructions that require this issue to be fixed (the instructions are identical except for the address type operand). gas/ChangeLog: * config/tc-arc.c (find_opcode_match): Use insert function to validate matching address type operands. * testsuite/gas/arc/nps400-10.d: New file. * testsuite/gas/arc/nps400-10.s: New file. opcodes/ChangeLog: * arc-opc.c (arc_flag_operands): Add F_DI14. (arc_flag_classes): Add C_DI14. * arc-nps400-tbl.h: Add new exc instructions.
Diffstat (limited to 'opcodes/arc-nps400-tbl.h')
-rw-r--r--opcodes/arc-nps400-tbl.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h
index 8585450..bfc2dee 100644
--- a/opcodes/arc-nps400-tbl.h
+++ b/opcodes/arc-nps400-tbl.h
@@ -713,3 +713,17 @@ XLDST_LIKE("xst", 0xe)
/* dcmac a,[cm:A],[cm:b],size */
{ "dcmac", 0x500007c023000000, 0xf80007ffffc00000, ARC_OPCODE_ARC700, PROTOCOL_DECODE, NPS400, { NPS_RA_64, BRAKET, NPS_CM, COLON, NPS_UIMM16_0_64, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_RBdouble_64, BRAKETdup, NPS_PROTO_SIZE }, { 0 }},
+
+/* Atomic Operations. */
+
+/* exc<.di><.f> a,a,[xa:b] */
+{ "exc", 0x48060c21, 0xf80fbfff, ARC_OPCODE_ARC700, NONE, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_XA, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }},
+
+/* exc<.di><.f> a,a,[sd:b] */
+{ "exc", 0x48060c61, 0xf80fbfff, ARC_OPCODE_ARC700, NONE, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_SD, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }},
+
+/* exc<.di><.f> a,a,[xd:b] */
+{ "exc", 0x48060c81, 0xf80fbfff, ARC_OPCODE_ARC700, NONE, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_XD, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }},
+
+/* exc<.di><.f> a,a,[b] */
+{ "exc", 0x48060c01, 0xf80fbfff, ARC_OPCODE_ARC700, NONE, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }},