New ARC implementation.

bfd	* archures.c: Remove support for older ARC. Added support for new
	ARC cpus (ARC600, ARC601, ARC700, ARCV2).
	* bfd-in2.h: Likewise.
	* config.bfd: Likewise.
	* cpu-arc.c: Likewise.
	* elf32-arc.c: Totally changed file with a refactored
	inplementation of the ARC port.
	* libbfd.h: Added ARC specific relocation types.
	* reloc.c: Likewise.

gas     * config/tc-arc.c: Revamped file for ARC support.
        * config/tc-arc.h: Likewise.
        * doc/as.texinfo: Add new ARC options.
        * doc/c-arc.texi: Likewise.

ld	* configure.tgt: Added target arc-*-elf* and arc*-*-linux-uclibc*.
	* emulparams/arcebelf_prof.sh: New file
	* emulparams/arcebelf.sh: Likewise.
	* emulparams/arceblinux_prof.sh: Likewise.
	* emulparams/arceblinux.sh: Likewise.
	* emulparams/arcelf_prof.sh: Likewise.
	* emulparams/arcelf.sh: Likewise.
	* emulparams/arclinux_prof.sh: Likewise.
	* emulparams/arclinux.sh: Likewise.
	* emulparams/arcv2elfx.sh: Likewise.
	* emulparams/arcv2elf.sh: Likewise.
	* emultempl/arclinux.em: Likewise.
	* scripttempl/arclinux.sc: Likewise.
	* scripttempl/elfarc.sc: Likewise.
	* scripttempl/elfarcv2.sc: Likewise
	* Makefile.am: Add new ARC emulations.
	* Makefile.in: Regenerate.
	* NEWS: Mention the new feature.

opcodes * arc-dis.c: Revamped file for ARC support
	* arc-dis.h: Likewise.
	* arc-ext.c: Likewise.
	* arc-ext.h: Likewise.
	* arc-opc.c: Likewise.
	* arc-fxi.h: New file.
	* arc-regs.h: Likewise.
	* arc-tbl.h: Likewise.

binutils * readelf.c (get_machine_name): Remove A5 reference. Add ARCompact
	and ARCv2.
	(get_machine_flags): Handle EM_ARCV2 and EM_ARCOMPACT.
	(guess_is_rela): Likewise.
	(dump_relocations): Likewise.
	(is_32bit_abs_reloc): Likewise.
	(is_16bit_abs_reloc): Likewise.
	(is_none_reloc): Likewise.
	* NEWS: Mention the new feature.

include	* dis-asm.h (arc_get_disassembler): Correct declaration.
	* arc-reloc.def: Macro file with definition of all relocation
	types.
	* arc.h: Changed macros for the newly supported ARC cpus.  Altered
	enum defining the supported relocations.
	* common.h: Changed EM_ARC_A5 definition to EM_ARC_COMPACT. Added
	macro for EM_ARC_COMPACT2.
        * arc-func.h: New file.
        * arc.h: Likewise.

1 files changed, 398 insertions, 160 deletions

diff --git a/opcodes/arc-ext.c b/opcodes/arc-ext.c
index d2b3f12..3267fb5 100644
--- a/opcodes/arc-ext.c
+++ b/opcodes/arc-ext.c
@@ -1,4 +1,4 @@
-/* ARC target-dependent stuff. Extension structure access functions
+/* ARC target-dependent stuff.  Extension structure access functions
    Copyright (C) 1995-2015 Free Software Foundation, Inc.
 
    This file is part of libopcodes.
@@ -21,137 +21,88 @@
 #include "sysdep.h"
 #include <stdlib.h>
 #include <stdio.h>
+
 #include "bfd.h"
 #include "arc-ext.h"
+#include "elf/arc.h"
 #include "libiberty.h"
 
-/* Extension structure  */
-static struct arcExtMap arc_extension_map;
 
-/* Get the name of an extension instruction.  */
+/* This module provides support for extensions to the ARC processor
+   architecture.  */
 
-const char *
-arcExtMap_instName(int opcode, int minor, int *flags)
-{
-    if (opcode == 3)
-      {
-	/* FIXME: ??? need to also check 0/1/2 in bit0 for (3f) brk/sleep/swi  */
-	if (minor < 0x09 || minor == 0x3f)
-	  return 0;
-	else
-	  opcode = 0x1f - 0x10 + minor - 0x09 + 1;
-      }
-    else
-      if (opcode < 0x10)
-	return 0;
-    else
-      opcode -= 0x10;
-    if (!arc_extension_map.instructions[opcode])
-      return 0;
-    *flags = arc_extension_map.instructions[opcode]->flags;
-    return arc_extension_map.instructions[opcode]->name;
-}
 
-/* Get the name of an extension core register.  */
+/* Local constants.  */
 
-const char *
-arcExtMap_coreRegName(int value)
-{
-  if (value < 32)
-    return 0;
-  return arc_extension_map.coreRegisters[value-32];
-}
+#define FIRST_EXTENSION_CORE_REGISTER   32
+#define LAST_EXTENSION_CORE_REGISTER    59
+#define FIRST_EXTENSION_CONDITION_CODE  0x10
+#define LAST_EXTENSION_CONDITION_CODE   0x1f
 
-/* Get the name of an extension condition code.  */
+#define NUM_EXT_CORE      \
+  (LAST_EXTENSION_CORE_REGISTER  - FIRST_EXTENSION_CORE_REGISTER  + 1)
+#define NUM_EXT_COND      \
+  (LAST_EXTENSION_CONDITION_CODE - FIRST_EXTENSION_CONDITION_CODE + 1)
+#define INST_HASH_BITS    6
+#define INST_HASH_SIZE    (1 << INST_HASH_BITS)
+#define INST_HASH_MASK    (INST_HASH_SIZE - 1)
 
-const char *
-arcExtMap_condCodeName(int value)
-{
-  if (value < 16)
-    return 0;
-  return arc_extension_map.condCodes[value-16];
-}
 
-/* Get the name of an extension aux register.  */
+/* Local types.  */
 
-const char *
-arcExtMap_auxRegName(long address)
-{
-  /* walk the list of aux reg names and find the name  */
-  struct ExtAuxRegister *r;
+/* These types define the information stored in the table.  */
 
-  for (r = arc_extension_map.auxRegisters; r; r = r->next) {
-    if (r->address == address)
-      return (const char *) r->name;
-  }
-  return 0;
-}
+struct ExtInstruction
+{
+  char			 major;
+  char			 minor;
+  char			 flags;
+  char*			 name;
+  struct ExtInstruction* next;
+};
+
+struct ExtAuxRegister
+{
+  long			 address;
+  char*			 name;
+  struct ExtAuxRegister* next;
+};
 
-/* Recursively free auxilliary register strcture pointers until
-   the list is empty.  */
+struct ExtCoreRegister
+{
+  short		    number;
+  enum ExtReadWrite rw;
+  char*		    name;
+};
 
-static void
-clean_aux_registers(struct ExtAuxRegister *r)
+struct arcExtMap
 {
-  if (r -> next)
-    {
-      clean_aux_registers( r->next);
-      free(r -> name);
-      free(r -> next);
-      r ->next = NULL;
-    }
-  else
-    free(r -> name);
-}
+  struct ExtAuxRegister* auxRegisters;
+  struct ExtInstruction* instructions[INST_HASH_SIZE];
+  struct ExtCoreRegister coreRegisters[NUM_EXT_CORE];
+  char*			 condCodes[NUM_EXT_COND];
+};
 
-/* Free memory that has been allocated for the extensions.  */
 
-static void
-cleanup_ext_map(void)
-{
-  struct ExtAuxRegister *r;
-  struct ExtInstruction *insn;
-  int i;
+/* Local data.  */
 
-  /* clean aux reg structure  */
-  r = arc_extension_map.auxRegisters;
-  if (r)
-    {
-      (clean_aux_registers(r));
-      free(r);
-    }
+/* Extension table.  */
+static struct arcExtMap arc_extension_map;
 
-  /* clean instructions  */
-  for (i = 0; i < NUM_EXT_INST; i++)
-    {
-      insn = arc_extension_map.instructions[i];
-      if (insn)
-	free(insn->name);
-    }
 
-  /* clean core reg struct  */
-  for (i = 0; i < NUM_EXT_CORE; i++)
-    {
-      if (arc_extension_map.coreRegisters[i])
-	free(arc_extension_map.coreRegisters[i]);
-    }
+/* Local macros.  */
 
-  for (i = 0; i < NUM_EXT_COND; i++) {
-    if (arc_extension_map.condCodes[i])
-      free(arc_extension_map.condCodes[i]);
-  }
+/* A hash function used to map instructions into the table.  */
+#define INST_HASH(MAJOR, MINOR)    ((((MAJOR) << 3) ^ (MINOR)) & INST_HASH_MASK)
 
-  memset(&arc_extension_map, 0, sizeof(struct arcExtMap));
-}
 
-int
-arcExtMap_add(void *base, unsigned long length)
-{
-  unsigned char *block = (unsigned char *) base;
-  unsigned char *p = (unsigned char *) block;
+/* Local functions.  */
 
-  /* Clean up and reset everything if needed.  */
-  cleanup_ext_map();
+static void
+create_map (unsigned char *block,
+	    unsigned long length)
+{
+  unsigned char *p = block;
 
   while (p && p < (block + length))
     {
@@ -165,97 +116,384 @@ arcExtMap_add(void *base, unsigned long length)
 	 For core regs and condition codes:
 	   p[2]  = value
 	   p[3]+ = name
-	 For aux regs:
+	 For auxiliary regs:
 	   p[2..5] = value
 	   p[6]+   = name
-	 (value is p[2]<<24|p[3]<<16|p[4]<<8|p[5])  */
+	     (value is p[2]<<24|p[3]<<16|p[4]<<8|p[5]).  */
 
+      /* The sequence of records is temrinated by an "empty"
+	 record.  */
       if (p[0] == 0)
-	return -1;
+	break;
 
       switch (p[1])
 	{
 	case EXT_INSTRUCTION:
 	  {
-	    char opcode = p[2];
-	    char minor  = p[3];
-	    char * insn_name = (char *) xmalloc(( (int)*p-5) * sizeof(char));
-	    struct ExtInstruction * insn =
-	      (struct ExtInstruction *) xmalloc(sizeof(struct ExtInstruction));
-
-	    if (opcode==3)
-	      opcode = 0x1f - 0x10 + minor - 0x09 + 1;
-	    else
-	      opcode -= 0x10;
-	    insn -> flags = (char) *(p+4);
-	    strcpy (insn_name, (char *) (p+5));
-	    insn -> name = insn_name;
-	    arc_extension_map.instructions[(int) opcode] = insn;
+	    struct ExtInstruction  *insn = XNEW (struct ExtInstruction);
+	    int			    major = p[2];
+	    int			    minor = p[3];
+	    struct ExtInstruction **bucket =
+		   &arc_extension_map.instructions[INST_HASH (major, minor)];
+
+	    insn->name  = xstrdup ((char *) (p + 5));
+	    insn->major = major;
+	    insn->minor = minor;
+	    insn->flags = p[4];
+	    insn->next  = *bucket;
+	    *bucket = insn;
+	    break;
 	  }
-	  break;
 
 	case EXT_CORE_REGISTER:
 	  {
-	    char * core_name = (char *) xmalloc(((int)*p-3) * sizeof(char));
+	    unsigned char number = p[2];
+	    char*	  name	 = (char *) (p + 3);
+
+	    arc_extension_map.
+	      coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].number
+	      = number;
+	    arc_extension_map.
+	      coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].rw
+	      = REG_READWRITE;
+	    arc_extension_map.
+	      coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].name
+	      = xstrdup (name);
+	    break;
+	  }
 
-	    strcpy(core_name, (char *) (p+3));
-	    arc_extension_map.coreRegisters[p[2]-32] = core_name;
+	case EXT_LONG_CORE_REGISTER:
+	  {
+	    unsigned char     number = p[2];
+	    char*	      name   = (char *) (p + 7);
+	    enum ExtReadWrite rw     = p[6];
+
+	    arc_extension_map.
+	      coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].number
+	      = number;
+	    arc_extension_map.
+	      coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].rw
+	      = rw;
+	    arc_extension_map.
+	      coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].name
+	      = xstrdup (name);
 	  }
-	  break;
 
 	case EXT_COND_CODE:
 	  {
-	    char * cc_name = (char *) xmalloc( ((int)*p-3) * sizeof(char));
-	    strcpy(cc_name, (char *) (p+3));
-	    arc_extension_map.condCodes[p[2]-16] = cc_name;
+	    char *cc_name = xstrdup ((char *) (p + 3));
+
+	    arc_extension_map.
+	      condCodes[p[2] - FIRST_EXTENSION_CONDITION_CODE]
+	      = cc_name;
+	    break;
 	  }
-	  break;
 
 	case EXT_AUX_REGISTER:
 	  {
-	    /* trickier -- need to store linked list to these  */
-	    struct ExtAuxRegister *newAuxRegister =
-	      (struct ExtAuxRegister *)malloc(sizeof(struct ExtAuxRegister));
-	    char * aux_name = (char *) xmalloc ( ((int)*p-6) * sizeof(char));
+	    /* Trickier -- need to store linked list of these.  */
+	    struct ExtAuxRegister *newAuxRegister
+	      = XNEW (struct ExtAuxRegister);
+	    char *aux_name = xstrdup ((char *) (p + 6));
 
-	    strcpy (aux_name, (char *) (p+6));
 	    newAuxRegister->name = aux_name;
-	    newAuxRegister->address = p[2]<<24 | p[3]<<16 | p[4]<<8  | p[5];
+	    newAuxRegister->address = (p[2] << 24) | (p[3] << 16)
+	      | (p[4] << 8) | p[5];
 	    newAuxRegister->next = arc_extension_map.auxRegisters;
 	    arc_extension_map.auxRegisters = newAuxRegister;
+	    break;
 	  }
-	  break;
 
 	default:
-	  return -1;
+	  break;
+	}
+
+      p += p[0]; /* Move on to next record.  */
+    }
+}
+
+
+/* Free memory that has been allocated for the extensions.  */
+
+static void
+destroy_map (void)
+{
+  struct ExtAuxRegister *r;
+  unsigned int		 i;
+
+  /* Free auxiliary registers.  */
+  r = arc_extension_map.auxRegisters;
+  while (r)
+    {
+      /* N.B. after r has been freed, r->next is invalid!  */
+      struct ExtAuxRegister* next = r->next;
+
+      free (r->name);
+      free (r);
+      r = next;
+    }
+
+  /* Free instructions.  */
+  for (i = 0; i < INST_HASH_SIZE; i++)
+    {
+      struct ExtInstruction *insn = arc_extension_map.instructions[i];
+
+      while (insn)
+	{
+	  /* N.B. after insn has been freed, insn->next is invalid!  */
+	  struct ExtInstruction *next = insn->next;
+
+	  free (insn->name);
+	  free (insn);
+	  insn = next;
+	}
+    }
+
+  /* Free core registers.  */
+  for (i = 0; i < NUM_EXT_CORE; i++)
+    {
+      if (arc_extension_map.coreRegisters[i].name)
+	free (arc_extension_map.coreRegisters[i].name);
+    }
 
+  /* Free condition codes.  */
+  for (i = 0; i < NUM_EXT_COND; i++)
+    {
+      if (arc_extension_map.condCodes[i])
+	free (arc_extension_map.condCodes[i]);
+    }
+
+  memset (&arc_extension_map, 0, sizeof (arc_extension_map));
+}
+
+
+static const char *
+ExtReadWrite_image (enum ExtReadWrite val)
+{
+    switch (val)
+    {
+	case REG_INVALID  : return "INVALID";
+	case REG_READ	  : return "RO";
+	case REG_WRITE	  : return "WO";
+	case REG_READWRITE: return "R/W";
+	default		  : return "???";
+    }
+}
+
+
+/* Externally visible functions.  */
+
+/* Get the name of an extension instruction.  */
+
+const char *
+arcExtMap_instName (int opcode,
+		    int insn,
+		    int *flags)
+{
+  /* Here the following tasks need to be done.  First of all, the
+     opcode stored in the Extension Map is the real opcode.  However,
+     the subopcode stored in the instruction to be disassembled is
+     mangled.  We pass (in minor opcode), the instruction word.  Here
+     we will un-mangle it and get the real subopcode which we can look
+     for in the Extension Map.  This function is used both for the
+     ARCTangent and the ARCompact, so we would also need some sort of
+     a way to distinguish between the two architectures.  This is
+     because the ARCTangent does not do any of this mangling so we
+     have no issues there.  */
+
+  /* If P[22:23] is 0 or 2 then un-mangle using iiiiiI.  If it is 1
+     then use iiiiIi.  Now, if P is 3 then check M[5:5] and if it is 0
+     then un-mangle using iiiiiI else iiiiii.  */
+
+  unsigned char minor;
+  struct ExtInstruction *temp;
+
+  /* 16-bit instructions.  */
+  if (0x08 <= opcode && opcode <= 0x0b)
+    {
+      unsigned char b, c, i;
+
+      b = (insn & 0x0700) >> 8;
+      c = (insn & 0x00e0) >> 5;
+      i = (insn & 0x001f);
+
+      if (i)
+	minor = i;
+      else
+	minor = (c == 0x07) ? b : c;
+    }
+  /* 32-bit instructions.  */
+  else
+    {
+      unsigned char I, A, B;
+
+      I = (insn & 0x003f0000) >> 16;
+      A = (insn & 0x0000003f);
+      B = ((insn & 0x07000000) >> 24) | ((insn & 0x00007000) >> 9);
+
+      if (I != 0x2f)
+	{
+#ifndef UNMANGLED
+	  switch (P)
+	    {
+	    case 3:
+	      if (M)
+		{
+		  minor = I;
+		  break;
+		}
+	    case 0:
+	    case 2:
+	      minor = (I >> 1) | ((I & 0x1) << 5);
+	      break;
+	    case 1:
+	      minor = (I >> 1) | (I & 0x1) | ((I & 0x2) << 4);
+	    }
+#else
+	  minor = I;
+#endif
+	}
+      else
+	{
+	  if (A != 0x3f)
+	    minor = A;
+	  else
+	    minor = B;
+	}
+    }
+
+  temp = arc_extension_map.instructions[INST_HASH (opcode, minor)];
+  while (temp)
+    {
+      if ((temp->major == opcode) && (temp->minor == minor))
+	{
+	  *flags = temp->flags;
+	  return temp->name;
 	}
-      p += p[0]; /* move to next record  */
+      temp = temp->next;
     }
 
-  return 0;
+  return NULL;
 }
 
-/* Load hw extension descibed in .extArcMap ELF section.  */
+/* Get the name of an extension core register.  */
 
-void
-build_ARC_extmap (text_bfd)
-  bfd *text_bfd;
+const char *
+arcExtMap_coreRegName (int regnum)
+{
+  if (regnum < FIRST_EXTENSION_CORE_REGISTER
+      || regnum > LAST_EXTENSION_CONDITION_CODE)
+    return NULL;
+  return arc_extension_map.
+    coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].name;
+}
+
+/* Get the access mode of an extension core register.  */
+
+enum ExtReadWrite
+arcExtMap_coreReadWrite (int regnum)
 {
-  char *arcExtMap;
-  bfd_size_type count;
-  asection *p;
+  if (regnum < FIRST_EXTENSION_CORE_REGISTER
+      || regnum > LAST_EXTENSION_CONDITION_CODE)
+    return REG_INVALID;
+  return arc_extension_map.
+    coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].rw;
+}
+
+/* Get the name of an extension condition code.  */
+
+const char *
+arcExtMap_condCodeName (int code)
+{
+  if (code < FIRST_EXTENSION_CONDITION_CODE
+      || code > LAST_EXTENSION_CONDITION_CODE)
+    return NULL;
+  return arc_extension_map.
+    condCodes[code - FIRST_EXTENSION_CONDITION_CODE];
+}
+
+/* Get the name of an extension auxiliary register.  */
+
+const char *
+arcExtMap_auxRegName (long address)
+{
+  /* Walk the list of auxiliary register names and find the name.  */
+  struct ExtAuxRegister *r;
+
+  for (r = arc_extension_map.auxRegisters; r; r = r->next)
+    {
+      if (r->address == address)
+	return (const char *)r->name;
+    }
+  return NULL;
+}
+
+/* Load extensions described in .arcextmap and
+   .gnu.linkonce.arcextmap.* ELF section.  */
 
-  for (p = text_bfd->sections; p != NULL; p = p->next)
-    if (!strcmp (p->name, ".arcextmap"))
+void
+build_ARC_extmap (bfd *text_bfd)
+{
+  asection *sect;
+
+  /* The map is built each time gdb loads an executable file - so free
+     any existing map, as the map defined by the new file may differ
+     from the old.  */
+  destroy_map ();
+
+  for (sect = text_bfd->sections; sect != NULL; sect = sect->next)
+    if (!strncmp (sect->name,
+		  ".gnu.linkonce.arcextmap.",
+	  sizeof (".gnu.linkonce.arcextmap.") - 1)
+	|| !strcmp (sect->name,".arcextmap"))
       {
-        count = bfd_get_section_size (p);
-        arcExtMap = (char *) xmalloc (count);
-        if (bfd_get_section_contents (text_bfd, p, (PTR) arcExtMap, 0, count))
-          {
-            arcExtMap_add ((PTR) arcExtMap, count);
-            break;
-          }
-        free ((PTR) arcExtMap);
+	bfd_size_type  count  = bfd_get_section_size (sect);
+	unsigned char* buffer = xmalloc (count);
+
+	if (buffer)
+	  {
+	    if (bfd_get_section_contents (text_bfd, sect, buffer, 0, count))
+	      create_map (buffer, count);
+	    free (buffer);
+	  }
       }
 }
+
+
+void
+dump_ARC_extmap (void)
+{
+    struct ExtAuxRegister *r;
+    int			   i;
+
+    r = arc_extension_map.auxRegisters;
+
+    while (r)
+    {
+	printf ("AUX : %s %ld\n", r->name, r->address);
+	r = r->next;
+    }
+
+    for (i = 0; i < INST_HASH_SIZE; i++)
+    {
+	struct ExtInstruction *insn;
+
+	for (insn = arc_extension_map.instructions[i];
+	     insn != NULL; insn = insn->next)
+	    printf ("INST: %d %d %x %s\n", insn->major, insn->minor,
+		    insn->flags, insn->name);
+    }
+
+    for (i = 0; i < NUM_EXT_CORE; i++)
+    {
+	struct ExtCoreRegister reg = arc_extension_map.coreRegisters[i];
+
+	if (reg.name)
+	    printf ("CORE: %s %d %s\n", reg.name, reg.number,
+		    ExtReadWrite_image (reg.rw));
+    }
+
+    for (i = 0; i < NUM_EXT_COND; i++)
+	if (arc_extension_map.condCodes[i])
+	    printf ("COND: %s\n", arc_extension_map.condCodes[i]);
+}