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| author | Claudiu Zissulescu <claziss@synopsys.com> | 2016-09-14 13:40:38 +0200 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@synopsys.com> | 2016-09-26 16:47:17 +0200 |
| commit | 2b848ebdbb2d1f856c7525ed4d6efaf6fe70de81 (patch) | |
| tree | 55a6c5fb94d76ce44c2ec41f30a06f1daa427b5c /opcodes/arc-ext-tbl.h | |
| parent | 005d79fd6101dae0aaf62a1b0cee399efcbd0e21 (diff) | |
| download | gdb-2b848ebdbb2d1f856c7525ed4d6efaf6fe70de81.zip gdb-2b848ebdbb2d1f856c7525ed4d6efaf6fe70de81.tar.gz gdb-2b848ebdbb2d1f856c7525ed4d6efaf6fe70de81.tar.bz2 | |
[ARC] ISA alignment.
include/
2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (insn_class_t): Add two new classes.
opcodes/
2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
* arc-ext-tbl.h (EXTINSN2OPF): Define.
(EXTINSN2OP): Use EXTINSN2OPF.
(bspeekm, bspop, modapp): New extension instructions.
* arc-opc.c (F_DNZ_ND): Define.
(F_DNZ_D): Likewise.
(F_SIZEB1): Changed.
(C_DNZ_D): Define.
(C_HARD): Changed.
* arc-tbl.h (dbnz): New instruction.
(prealloc): Allow it for ARC EM.
(xbfu): Likewise.
Diffstat (limited to 'opcodes/arc-ext-tbl.h')
| -rw-r--r-- | opcodes/arc-ext-tbl.h | 23 |
1 files changed, 16 insertions, 7 deletions
diff --git a/opcodes/arc-ext-tbl.h b/opcodes/arc-ext-tbl.h index 3fb1c11..e77e968 100644 --- a/opcodes/arc-ext-tbl.h +++ b/opcodes/arc-ext-tbl.h @@ -55,19 +55,22 @@ #define ARG_32BIT_ZALIMM { ZA, LIMM } /* Macro to generate 2 operand extension instruction. */ -#define EXTINSN2OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ +#define EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FL) \ { NAME, INSN2OP_BC (MOP,SOP), MINSN2OP_BC, CPU, CLASS, SCLASS, \ - ARG_32BIT_RBRC, FLAGS_F }, \ + ARG_32BIT_RBRC, FL }, \ { NAME, INSN2OP_0C (MOP,SOP), MINSN2OP_0C, CPU, CLASS, SCLASS, \ - ARG_32BIT_ZARC, FLAGS_F }, \ + ARG_32BIT_ZARC, FL }, \ { NAME, INSN2OP_BU (MOP,SOP), MINSN2OP_BU, CPU, CLASS, SCLASS, \ - ARG_32BIT_RBU6, FLAGS_F }, \ + ARG_32BIT_RBU6, FL }, \ { NAME, INSN2OP_0U (MOP,SOP), MINSN2OP_0U, CPU, CLASS, SCLASS, \ - ARG_32BIT_ZAU6, FLAGS_F }, \ + ARG_32BIT_ZAU6, FL }, \ { NAME, INSN2OP_BL (MOP,SOP), MINSN2OP_BL, CPU, CLASS, SCLASS, \ - ARG_32BIT_RBLIMM, FLAGS_F }, \ + ARG_32BIT_RBLIMM, FL }, \ { NAME, INSN2OP_0L (MOP,SOP), MINSN2OP_0L, CPU, CLASS, SCLASS, \ - ARG_32BIT_ZALIMM, FLAGS_F }, + ARG_32BIT_ZALIMM, FL }, + +#define EXTINSN2OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ + EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FLAGS_F) /* Macro to generate 3 operand extesion instruction. */ #define EXTINSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ @@ -120,3 +123,9 @@ EXTINSN2OP ("dsp_fp_sqrt", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE, 7, 45) EXTINSN3OP ("dsp_fp_div", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE, 7, 42) EXTINSN3OP ("dsp_fp_cmp", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE, 7, 43) +/* Bitstream extensions. */ +EXTINSN2OP ("bspeek", ARC_OPCODE_ARCv2EM, BITSTREAM, NONE, 0x05, 0x2E) +EXTINSN2OP ("bspop", ARC_OPCODE_ARCv2EM, BITSTREAM, NONE, 0x05, 0x2F) + +/* Special XY. */ +EXTINSN2OPF ("modapp", ARC_OPCODE_ARCv2EM, XY, NONE, 0x05, 0x3E, FLAGS_NONE) |