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| author | Claudiu Zissulescu <claziss@synopsys.com> | 2016-05-19 12:19:32 +0200 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@synopsys.com> | 2016-05-23 17:41:54 +0200 |
| commit | d9eca1df01c0e6f7f22566c154e63b1df9315790 (patch) | |
| tree | 62db0f1f82fd7eee47f44d2fbff0174895096100 /opcodes/arc-dis.c | |
| parent | 87789e08e5cb2191af1122ed98af2d6c023b3a0a (diff) | |
| download | gdb-d9eca1df01c0e6f7f22566c154e63b1df9315790.zip gdb-d9eca1df01c0e6f7f22566c154e63b1df9315790.tar.gz gdb-d9eca1df01c0e6f7f22566c154e63b1df9315790.tar.bz2 | |
[ARC] Update instruction type and delay slot info.
This patch corrects the instructioninformation passed into the
disassebler_info structure.
include/
2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (insn_subclass_t): Add COND.
(flag_class_t): Add F_CLASS_EXTEND.
opcodes/
2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
information.
(print_insn_arc): Set insn_type information.
* arc-opc.c (C_CC): Add F_CLASS_COND.
* arc-tbl.h (bbit0, bbit1): Update subclass to COND.
(beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
(ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
(breq, breq_s, brge, brhs, brlo, brlt): Likewise.
(brne, brne_s, jeq_s, jne_s): Likewise.
Diffstat (limited to 'opcodes/arc-dis.c')
| -rw-r--r-- | opcodes/arc-dis.c | 31 |
1 files changed, 25 insertions, 6 deletions
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c index 96fd092..3953667 100644 --- a/opcodes/arc-dis.c +++ b/opcodes/arc-dis.c @@ -270,12 +270,21 @@ print_flags (const struct arc_opcode *opcode, break; } } + if (flg_operand->name[0] == 'd' + && flg_operand->name[1] == 0) + info->branch_delay_insns = 1; + + /* Check if it is a conditional flag. */ + if (cl_flags->flag_class & F_CLASS_COND) + { + if (info->insn_type == dis_jsr) + info->insn_type = dis_condjsr; + else if (info->insn_type == dis_branch) + info->insn_type = dis_condbranch; + } + (*info->fprintf_func) (info->stream, "%s", flg_operand->name); } - - if (flg_operand->name[0] == 'd' - && flg_operand->name[1] == 0) - info->branch_delay_insns = 1; } } } @@ -533,9 +542,19 @@ print_insn_arc (bfd_vma memaddr, case JUMP: if (!strncmp (opcode->name, "bl", 2) || !strncmp (opcode->name, "jl", 2)) - info->insn_type = dis_jsr; + { + if (opcode->subclass == COND) + info->insn_type = dis_condjsr; + else + info->insn_type = dis_jsr; + } else - info->insn_type = dis_branch; + { + if (opcode->subclass == COND) + info->insn_type = dis_condbranch; + else + info->insn_type = dis_branch; + } break; case MEMORY: info->insn_type = dis_dref; /* FIXME! DB indicates mov as memory! */ |