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| author | Matthew Wahab <matthew.wahab@arm.com> | 2015-12-14 17:22:36 +0000 |
|---|---|---|
| committer | Matthew Wahab <matthew.wahab@arm.com> | 2015-12-14 17:22:36 +0000 |
| commit | 4b5fc357a17d59929cf39869d19fc4eabdb7ae81 (patch) | |
| tree | 28879571174ad092bdbd634be9edf57f203be034 /opcodes/aarch64-tbl.h | |
| parent | bb515fea4ac30f761c17dec701c95c0b54fabf30 (diff) | |
| download | gdb-4b5fc357a17d59929cf39869d19fc4eabdb7ae81.zip gdb-4b5fc357a17d59929cf39869d19fc4eabdb7ae81.tar.gz gdb-4b5fc357a17d59929cf39869d19fc4eabdb7ae81.tar.bz2 | |
[AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds an FP16
instruction to the group Adv.SIMD Modified Immediate, making it
available when +simd+fp16 is enabled.
The instruction added is: FMOV.
The form of this instructions is
<OP> <Hd>, #<imm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD modified immediate
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SIMD_IMM_H): New.
(aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD
modified immediate group.
Change-Id: Ic66af44c494e6a53fb1cf01c372cdc62d12643e2
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index a7ce31a..0481b7d 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1313,6 +1313,13 @@ QLF2(S_D, NIL), \ } +/* e.g. FMOV <Vd>.<T>, #<imm>. */ +#define QL_SIMD_IMM_H \ +{ \ + QLF2 (V_4H, NIL), \ + QLF2 (V_8H, NIL), \ +} + /* e.g. MOVI <Vd>.2D, #<imm>. */ #define QL_SIMD_IMM_V2D \ { \ @@ -1518,6 +1525,8 @@ struct aarch64_opcode aarch64_opcode_table[] = {"movi", 0xf00c400, 0xbff8ec00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ}, {"movi", 0xf00e400, 0xbff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_B, F_SIZEQ}, {"fmov", 0xf00f400, 0xbff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_S, F_SIZEQ}, + {"fmov", 0xf00fc00, 0xbff8fc00, asimdimm, 0, SIMD_F16, + OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_H, F_SIZEQ}, {"mvni", 0x2f000400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ}, {"bic", 0x2f001400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ}, {"mvni", 0x2f008400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ}, |