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| author | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2016-11-18 09:58:38 +0000 |
|---|---|---|
| committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2016-11-18 09:58:38 +0000 |
| commit | 28617675c264213180a599bb4327bf162029636a (patch) | |
| tree | 0e8b93d7256db9f08ae5e6a0afdb431d4718b50c /opcodes/aarch64-tbl.h | |
| parent | ccfc90a39b78b7bc4173cd9ead49d2aa59695378 (diff) | |
| download | gdb-28617675c264213180a599bb4327bf162029636a.zip gdb-28617675c264213180a599bb4327bf162029636a.tar.gz gdb-28617675c264213180a599bb4327bf162029636a.tar.bz2 | |
[AArch64] Add ARMv8.3 weaker release consistency load instructions
Add support for ARMv8.3 LDAPRB, LDAPRH and LDAPR weak release
consistency load instructions. (They are equivalent to LDARB,
LDARH and LDAR instructions other than the weaker memory ordering
requirement.)
For more details about weak release consistency see
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions
opcodes/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
gas/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Add ldaprb, ldaprh, ldapr tests.
* testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Likewise.
* testsuite/gas/aarch64/illegal-ldapr.s: Likewise.
* testsuite/gas/aarch64/illegal-ldapr.d: Likewise.
* testsuite/gas/aarch64/illegal-ldapr.l: Likewise.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index eb1274b..6960a56 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2958,6 +2958,9 @@ struct aarch64_opcode aarch64_opcode_table[] = CORE_INSN ("ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q), CORE_INSN ("stlr", 0x889ffc00, 0xbfe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), CORE_INSN ("ldar", 0x88dffc00, 0xbfeffc00, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), + V8_3_INSN ("ldaprb", 0x38bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), + V8_3_INSN ("ldaprh", 0x78bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), + V8_3_INSN ("ldapr", 0xb8bfc000, 0xbffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), /* Limited Ordering Regions load/store instructions. */ _LOR_INSN ("ldlar", 0x88df7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), _LOR_INSN ("ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), |