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| author | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:12 +0100 |
|---|---|---|
| committer | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:12 +0100 |
| commit | 7ce2460a77a8f66a145c11522f494f3262255390 (patch) | |
| tree | 74a65e3d48ac6927214a1e2b8b555b908fed7ccd /opcodes/aarch64-tbl.h | |
| parent | dd3189990b1d918b3a9e482ec6e9cc9a8b9e8fe9 (diff) | |
| download | gdb-7ce2460a77a8f66a145c11522f494f3262255390.zip gdb-7ce2460a77a8f66a145c11522f494f3262255390.tar.gz gdb-7ce2460a77a8f66a145c11522f494f3262255390.tar.bz2 | |
[binutils][aarch64] SVE2 feature extension flags.
Include all feature flag macros.
The "sve2" extension that enables the core sve2 instructions.
This also enables the sve extension, since sve is a requirement of sve2.
Extra optional sve2 features are the bitperm, sm4, aes, and sha3 extensions.
These are all given extra feature flags, "bitperm", "sve2-sm4",
"sve2-aes", and "sve2-sha3" respectively.
The sm4, aes, and sha3 extensions are explicitly marked as sve2
extensions to distinguish them from the corresponding NEON extensions.
Rather than continue extending the current feature flag numbers, I used
some bits that have been skipped.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c: Add command line architecture feature flags
"sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm".
* doc/c-aarch64.texi: Document new architecture feature flags.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SVE2
AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM,
AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New
feature macros.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-tbl.h
(aarch64_feature_sve2, aarch64_feature_sve2aes,
aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
aarch64_feature_sve2bitperm): New feature sets.
(SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
for feature set addresses.
(SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 9537ec5..481caea 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2206,6 +2206,16 @@ static const aarch64_feature_set aarch64_feature_memtag = AARCH64_FEATURE (AARCH64_FEATURE_V8_5 | AARCH64_FEATURE_MEMTAG, 0); static const aarch64_feature_set aarch64_feature_tme = AARCH64_FEATURE (AARCH64_FEATURE_TME, 0); +static const aarch64_feature_set aarch64_feature_sve2 = + AARCH64_FEATURE (AARCH64_FEATURE_SVE2, 0); +static const aarch64_feature_set aarch64_feature_sve2aes = + AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_AES, 0); +static const aarch64_feature_set aarch64_feature_sve2sha3 = + AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_SHA3, 0); +static const aarch64_feature_set aarch64_feature_sve2sm4 = + AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_SM4, 0); +static const aarch64_feature_set aarch64_feature_sve2bitperm = + AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_BITPERM, 0); #define CORE &aarch64_feature_v8 @@ -2242,6 +2252,11 @@ static const aarch64_feature_set aarch64_feature_tme = #define BTI &aarch64_feature_bti #define MEMTAG &aarch64_feature_memtag #define TME &aarch64_feature_tme +#define SVE2 &aarch64_feature_sve2 +#define SVE2_AES &aarch64_feature_sve2aes +#define SVE2_SHA3 &aarch64_feature_sve2sha3 +#define SVE2_SM4 &aarch64_feature_sve2sm4 +#define SVE2_BITPERM &aarch64_feature_sve2bitperm #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } @@ -2311,6 +2326,27 @@ static const aarch64_feature_set aarch64_feature_tme = { NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS, 0, 0, NULL } #define _TME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS, 0, 0, NULL } +#define SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \ + FLAGS | F_STRICT, 0, TIED, NULL } +#define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \ + FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } +#define SVE2AES_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SVE2_AES, OPS, QUALS, \ + FLAGS | F_STRICT, 0, TIED, NULL } +#define SVE2SHA3_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SVE2_SHA3, OPS, QUALS, \ + FLAGS | F_STRICT, 0, TIED, NULL } +#define SVE2SM4_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SVE2_SM4, OPS, QUALS, \ + FLAGS | F_STRICT, 0, TIED, NULL } +#define SVE2SM4_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SVE2_SM4, OPS, QUALS, \ + FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } +#define SVE2BITPERM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \ + FLAGS | F_STRICT, 0, TIED, NULL } struct aarch64_opcode aarch64_opcode_table[] = { |