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| author | Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com> | 2018-06-08 14:02:52 +0100 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2018-06-08 14:04:11 +0100 |
| commit | cb36699271e2f3308b6f1aa40086950111308020 (patch) | |
| tree | 806a477ee2d12682bdb752667418036ef95e76cb /opcodes/aarch64-tbl.h | |
| parent | fd161d860f1df7140153eab4726705cc3e2727b0 (diff) | |
| download | gdb-cb36699271e2f3308b6f1aa40086950111308020.zip gdb-cb36699271e2f3308b6f1aa40086950111308020.tar.gz gdb-cb36699271e2f3308b6f1aa40086950111308020.tar.bz2 | |
Prevent undefined FMOV instructions being accepted by the AArch64 assembler.
Detect illegal FMOV instructions that changes the size from 32 bits to 64
bits and vice versa. Add tests for these and other undefined FMOV
instructions.
PR 20319
gas * testsuite/gas/aarch64/illegal-3.s: Test if unallocated FMOV encodings
are detected as undefined.
* testsuite/gas/aarch64/illegal-3.d: Likewise.
* testsuite/gas/aarch64/illegal.s: Test if FMOV instructions that are
changing the size from 32 bits to 64 bits and vice versa trigger an
error.
* testsuite/gas/aarch64/illegal.l: Likewise.
opcodes * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
(aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index b416ded..1a35b3f 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -295,6 +295,13 @@ QLF2(S_S,X), \ } +/* e.g. FMOV <Dd>, <Xn>. */ +#define QL_INT2FP_FMOV \ +{ \ + QLF2(S_S,W), \ + QLF2(S_D,X), \ +} + /* e.g. SCVTF <Hd>, <Wn>. */ #define QL_INT2FP_H \ { \ @@ -311,6 +318,13 @@ QLF2(X,S_S), \ } +/* e.g. FMOV <Xd>, <Dn>. */ +#define QL_FP2INT_FMOV \ +{ \ + QLF2(W,S_S), \ + QLF2(X,S_D), \ +} + /* e.g. FCVTNS <Hd>, <Wn>. */ #define QL_FP2INT_H \ { \ @@ -3038,9 +3052,9 @@ struct aarch64_opcode aarch64_opcode_table[] = FF16_INSN ("fcvtas",0x1ee40000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), __FP_INSN ("fcvtau",0x1e250000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), FF16_INSN ("fcvtau",0x1ee50000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), - __FP_INSN ("fmov", 0x1e260000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), + __FP_INSN ("fmov", 0x1e260000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT_FMOV, F_FPTYPE | F_SF), FF16_INSN ("fmov", 0x1ee60000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), - __FP_INSN ("fmov", 0x1e270000, 0x7f3ffc00, float2int, 0, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF), + __FP_INSN ("fmov", 0x1e270000, 0x7f3ffc00, float2int, 0, OP2 (Fd, Rn), QL_INT2FP_FMOV, F_FPTYPE | F_SF), FF16_INSN ("fmov", 0x1ee70000, 0x7f3ffc00, float2int, OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF), __FP_INSN ("fcvtps",0x1e280000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), FF16_INSN ("fcvtps",0x1ee80000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), |