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| author | Tamar Christina <tamar.christina@arm.com> | 2018-06-22 12:27:53 +0100 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2018-06-22 12:32:19 +0100 |
| commit | 514cd3a0f589fa48ca7bc9504c36436c0cbefcb2 (patch) | |
| tree | 560f31954190dcc24cfcaadb07dfd9d90e070883 /opcodes/aarch64-tbl.h | |
| parent | bfd60e344c8001910825a358ad674003738ebb6b (diff) | |
| download | gdb-514cd3a0f589fa48ca7bc9504c36436c0cbefcb2.zip gdb-514cd3a0f589fa48ca7bc9504c36436c0cbefcb2.tar.gz gdb-514cd3a0f589fa48ca7bc9504c36436c0cbefcb2.tar.bz2 | |
Correct negs aliasing on AArch64.
This patch fixes a disassembly issue with the aliases to subs with a shifted
register. The subs instruction with the zero register as destination is
supposed to alias to cmp and when the first input register is the zero register
the subs is supposed to be aliased to negs.
This means that a subs with destination and first input registers the zero
register is supposed to be a cmp.
This is done by raising the priority of the cmp alias.
opcodes/
* aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
gas/
* testsuite/gas/aarch64/addsub.s: Add negs to zero reg test.
* testsuite/gas/aarch64/addsub.d: Likewise.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 1a35b3f..08eec60 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2266,7 +2266,7 @@ struct aarch64_opcode aarch64_opcode_table[] = CORE_INSN ("sub", 0x4b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), CORE_INSN ("neg", 0x4b0003e0, 0x7f2003e0, addsub_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), CORE_INSN ("subs", 0x6b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), - CORE_INSN ("cmp", 0x6b00001f, 0x7f20001f, addsub_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), + CORE_INSN ("cmp", 0x6b00001f, 0x7f20001f, addsub_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF | F_P1), CORE_INSN ("negs", 0x6b0003e0, 0x7f2003e0, addsub_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), /* AdvSIMD across lanes. */ SIMD_INSN ("saddlv", 0x0e303800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ), |