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| author | Yufeng Zhang <yufeng.zhang@arm.com> | 2013-01-17 16:09:44 +0000 |
|---|---|---|
| committer | Yufeng Zhang <yufeng.zhang@arm.com> | 2013-01-17 16:09:44 +0000 |
| commit | f5555712ba2c20a6fd30b789e497009646a4638d (patch) | |
| tree | 691b33edb086a7d1ae961993dff54b312aad5906 /opcodes/aarch64-tbl.h | |
| parent | be7d37a2c35f12d7fdcc9ad65333c0a81460cd89 (diff) | |
| download | gdb-f5555712ba2c20a6fd30b789e497009646a4638d.zip gdb-f5555712ba2c20a6fd30b789e497009646a4638d.tar.gz gdb-f5555712ba2c20a6fd30b789e497009646a4638d.tar.bz2 | |
include/opcode/
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
opcodes/
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
* aarch64-opc.c (operand_general_constraint_met_p): For
AARCH64_MOD_LSL, move the range check on the shift amount before the
alignment check; change to call set_sft_amount_out_of_range_error
instead of set_imm_out_of_range_error.
* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
SIMD_IMM_SFT.
gas/
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
* config/tc-aarch64.c (output_operand_error_record): Change to output
the out-of-range error message as value-expected message if there is
only one single value in the expected range.
(programmer_friendly_fixup): Remove the handling of 8-bit MOVI with
LSL #0 as a programmer-friendly feature.
gas/testsuite/
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/diagnostic.l: Update.
* gas/aarch64/movi.s: Add tests.
* gas/aarch64/movi.d: Update.
* gas/aarch64/programmer-friendly.s: Add comment.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index fd38a9d..e2906f8 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1171,11 +1171,11 @@ QLF2(V_4S, NIL), \ } -/* e.g. MOVI <Vd>.8B, #<imm8>. */ +/* e.g. MOVI <Vd>.8B, #<imm8> {, LSL #<amount>}. */ #define QL_SIMD_IMM_B \ { \ - QLF2(V_8B, NIL), \ - QLF2(V_16B, NIL), \ + QLF2(V_8B, LSL), \ + QLF2(V_16B, LSL), \ } /* e.g. MOVI <Dd>, #<imm>. */ #define QL_SIMD_IMM_D \ @@ -1341,7 +1341,7 @@ struct aarch64_opcode aarch64_opcode_table[] = {"movi", 0xf008400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ}, {"orr", 0xf009400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ}, {"movi", 0xf00c400, 0xbff8ec00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ}, - {"movi", 0xf00e400, 0xbff8fc00, asimdimm, OP_V_MOVI_B, SIMD, OP2 (Vd, SIMD_IMM), QL_SIMD_IMM_B, F_SIZEQ}, + {"movi", 0xf00e400, 0xbff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_B, F_SIZEQ}, {"fmov", 0xf00f400, 0xbff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_S, F_SIZEQ}, {"mvni", 0x2f000400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ}, {"bic", 0x2f001400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ}, |