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| author | Matthew Wahab <matthew.wahab@arm.com> | 2015-12-14 17:01:56 +0000 |
|---|---|---|
| committer | Matthew Wahab <matthew.wahab@arm.com> | 2015-12-14 17:01:56 +0000 |
| commit | 42f23f6218262ae8488caab214b7f272c6758941 (patch) | |
| tree | 60a1def1cbdc22e0858d3fab9f1952c83376f0dd /opcodes/aarch64-tbl.h | |
| parent | 80776b29d60ebdcd3631604858f144a72b8bcb8e (diff) | |
| download | gdb-42f23f6218262ae8488caab214b7f272c6758941.zip gdb-42f23f6218262ae8488caab214b7f272c6758941.tar.gz gdb-42f23f6218262ae8488caab214b7f272c6758941.tar.bz2 | |
[AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Indexed Element, making them available
when +simd+fp16 is enabled.
The instructions added are: FMLA, FMLS, FMUL and FMULX.
The general form for these instructions is
<OP> <V>.<T>, <V>.<T>, <V>.h[<idx>]
where T is 4h or 8h
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector indexed element
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_ELEMENT_FP_H): New.
(aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
fmulx to the vector indexed element group.
Change-Id: Ib70cd4eaa6ea2938f84ac41f31d72644dbb0ceb4
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index b2576e0..6c07c99 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1259,6 +1259,13 @@ QLF3(V_2D, V_2D, S_D), \ } +/* e.g. FMLA <V><d>, <V><n>, <Vm>.<Ts>[<index>]. */ +#define QL_ELEMENT_FP_H \ +{ \ + QLF3 (V_4H, V_4H, S_H), \ + QLF3 (V_8H, V_8H, S_H), \ +} + /* e.g. MOVI <Vd>.4S, #<imm8> {, LSL #<amount>}. */ #define QL_SIMD_IMM_S0W \ { \ @@ -1465,8 +1472,14 @@ struct aarch64_opcode aarch64_opcode_table[] = {"sqdmulh", 0xf00c000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ}, {"sqrdmulh", 0xf00d000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ}, {"fmla", 0xf801000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ}, + {"fmla", 0xf001000, 0xbfe0fc00, asimdelem, 0, SIMD_F16, + OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ}, {"fmls", 0xf805000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ}, + {"fmls", 0xf005000, 0xbfe0fc00, asimdelem, 0, SIMD_F16, + OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ}, {"fmul", 0xf809000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ}, + {"fmul", 0xf009000, 0xbfe0fc00, asimdelem, 0, SIMD_F16, + OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ}, {"mla", 0x2f000000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ}, {"umlal", 0x2f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ}, {"umlal2", 0x6f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ}, @@ -1476,6 +1489,8 @@ struct aarch64_opcode aarch64_opcode_table[] = {"umull", 0x2f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ}, {"umull2", 0x6f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ}, {"fmulx", 0x2f809000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ}, + {"fmulx", 0x2f009000, 0xbfe0fc00, asimdelem, 0, SIMD_F16, + OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ}, {"sqrdmlah", 0x2f00d000, 0xbf00f400, asimdelem, 0, RDMA, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ}, {"sqrdmlsh", 0x2f00f000, 0xbf00f400, asimdelem, 0, RDMA, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ}, /* AdvSIMD EXT. */ |