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| author | Matthew Wahab <matthew.wahab@arm.com> | 2015-12-10 14:05:01 +0000 |
|---|---|---|
| committer | Matthew Wahab <matthew.wahab@arm.com> | 2015-12-10 14:10:15 +0000 |
| commit | c8a6db6fa0b06b978e5b63593a6b0cb3300ad259 (patch) | |
| tree | f20dce99ea7b13923aa1e8b7f143aaef27d70126 /opcodes/aarch64-tbl.h | |
| parent | af117b3cf1877da805d081b93f606f3dd8153502 (diff) | |
| download | gdb-c8a6db6fa0b06b978e5b63593a6b0cb3300ad259.zip gdb-c8a6db6fa0b06b978e5b63593a6b0cb3300ad259.tar.gz gdb-c8a6db6fa0b06b978e5b63593a6b0cb3300ad259.tar.bz2 | |
[AArch64][PATCH 1/2] Add support for RAS instruction ESB.
The ARMv8.2 RAS extension adds a new barrier instruction ESB as an alias
and the preferred form of HINT 16.
This patch adds an architectural feature flag for the RAS extension and
includes it in the features selected enabled by -march=armv8.2-a. It
also adds the ESB instruction, making it available whenever the RAS
feature is enabled.
Because ESB is the preferred form and because the target architecture
isn't available to the disassembler, HINT 16 will be disassembled as ESB
even when the target has no support for the RAS extension.
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/system-2.d: New.
* gas/aarch64/system-2.s: New.
* gas/aarch64/system.d: Adjust expected output for HINT 16.
include/opcode/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (AARCH64_FEATURE_RAS): New.
(AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-tbl.h (aarch64_feature_ras): New.
(RAS): New.
(aarch64_opcode_table): Add "esb".
Change-Id: Id4713917da15cca3b977284f43febd1c9b3d9faf
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 50bbc2d..91d8dcf 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1297,6 +1297,8 @@ static const aarch64_feature_set aarch64_feature_lor = AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0); static const aarch64_feature_set aarch64_feature_rdma = AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0); +static const aarch64_feature_set aarch64_feature_ras = + AARCH64_FEATURE (AARCH64_FEATURE_RAS, 0); static const aarch64_feature_set aarch64_feature_v8_2 = AARCH64_FEATURE (AARCH64_FEATURE_V8_2, 0); static const aarch64_feature_set aarch64_feature_fp_f16 = @@ -1311,6 +1313,7 @@ static const aarch64_feature_set aarch64_feature_fp_f16 = #define LOR &aarch64_feature_lor #define RDMA &aarch64_feature_rdma #define FP_F16 &aarch64_feature_fp_f16 +#define RAS &aarch64_feature_ras #define ARMV8_2 &aarch64_feature_v8_2 struct aarch64_opcode aarch64_opcode_table[] = @@ -2456,6 +2459,7 @@ struct aarch64_opcode aarch64_opcode_table[] = {"wfi", 0xd503207f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS}, {"sev", 0xd503209f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS}, {"sevl", 0xd50320bf, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS}, + {"esb", 0xd503221f, 0xffffffff, ic_system, 0, RAS, OP0 (), {}, F_ALIAS}, {"clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, CORE, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)}, {"dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, CORE, OP1 (BARRIER), {}, 0}, {"dmb", 0xd50330bf, 0xfffff0ff, ic_system, 0, CORE, OP1 (BARRIER), {}, 0}, |