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| author | Matthew Wahab <matthew.wahab@arm.com> | 2015-12-14 17:16:50 +0000 |
|---|---|---|
| committer | Matthew Wahab <matthew.wahab@arm.com> | 2015-12-14 17:18:50 +0000 |
| commit | bb515fea4ac30f761c17dec701c95c0b54fabf30 (patch) | |
| tree | 1c5ddde0ea278a49008fc85b83ae530c5433146b /opcodes/aarch64-tbl.h | |
| parent | 5f7728b7413b3bed576f8dd11d1343c20b3a2333 (diff) | |
| download | gdb-bb515fea4ac30f761c17dec701c95c0b54fabf30.zip gdb-bb515fea4ac30f761c17dec701c95c0b54fabf30.tar.gz gdb-bb515fea4ac30f761c17dec701c95c0b54fabf30.tar.bz2 | |
[AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Adv.SIMD Across Lanes, making them available
when +simd+fp16 is enabled.
The instructions added are: FMAXNMV, FMAXV, FMINNMV and FMINV.
The general form for these instructions is
<OP> <Hd>, <V>.<T>
where T is 4h or 8h.
The new instructions valid make uses of the 8H and 4H that were
previously illegal. The patch adjusts a test for illegal uses of vector
types to take this into account.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes
instructions.
* gas/aarch64/illegal.d: Update expected output.
* gas/aarch64/illegal.s: Replace test for illegal use of 'h'
specifier.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_XLANES_FP_H): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv,
fminnmv, fminv to the Adv.SIMD across lanes group.
Change-Id: Ib9a47e867f55e0272c2446eb7e16837503d2f94c
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 17ab3c1..a7ce31a 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1218,6 +1218,13 @@ QLF2(S_S, V_4S), \ } +/* e.g. FMINV <V><d>, <Vn>.<T>. */ +#define QL_XLANES_FP_H \ +{ \ + QLF2 (S_H, V_4H), \ + QLF2 (S_H, V_8H), \ +} + /* e.g. SADDLV <V><d>, <Vn>.<T>. */ #define QL_XLANES_L \ { \ @@ -1397,9 +1404,17 @@ struct aarch64_opcode aarch64_opcode_table[] = {"umaxv", 0x2e30a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ}, {"uminv", 0x2e31a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ}, {"fmaxnmv", 0x2e30c800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ}, + {"fmaxnmv", 0xe30c800, 0xbffffc00, asimdall, 0, SIMD_F16, + OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ}, {"fmaxv", 0x2e30f800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ}, + {"fmaxv", 0xe30f800, 0xbffffc00, asimdall, 0, SIMD_F16, + OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ}, {"fminnmv", 0x2eb0c800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ}, + {"fminnmv", 0xeb0c800, 0xbffffc00, asimdall, 0, SIMD_F16, + OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ}, {"fminv", 0x2eb0f800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ}, + {"fminv", 0xeb0f800, 0xbffffc00, asimdall, 0, SIMD_F16, + OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ}, /* AdvSIMD three different. */ {"saddl", 0x0e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ}, {"saddl2", 0x4e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ}, |