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| author | Matthew Wahab <matthew.wahab@arm.com> | 2015-11-27 15:25:08 +0000 |
|---|---|---|
| committer | Matthew Wahab <matthew.wahab@arm.com> | 2015-11-27 15:28:42 +0000 |
| commit | d685192a58d4c198633bd0e69cfe0a114576e98a (patch) | |
| tree | 8b57e30467eb5a4d74ddf557c3822dd8f1016070 /opcodes/aarch64-tbl.h | |
| parent | e19616610d7327664f99215a69cb326682742dc3 (diff) | |
| download | gdb-d685192a58d4c198633bd0e69cfe0a114576e98a.zip gdb-d685192a58d4c198633bd0e69cfe0a114576e98a.tar.gz gdb-d685192a58d4c198633bd0e69cfe0a114576e98a.tar.bz2 | |
[AArch64] Add ARMv8.2 instructions BFC and REV64.
ARMv8.2 adds two new instructions: BFC as an alias for BFM and REV64 as
an alias for REV. This patch set adds support for these to binutils,
enabled when the -march=armv8.2-a is given. It depends on the support
for an instruction being its preferred form which was added in an
earlier patch.
This patch adds the alias BFC <Rd>, #<imm>, #<width> as the preferred
form for BFM when the source is a zero register and the conditions for
using the BFI form are met (in other words, BFC is the preferred form
for BFI <Rd>, <Rs>, #<imm>, #<width> when the <Rs> is a zero register).
gas/testsuite/
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/alias-2.d: New.
* gas/aarch64/alias-2.s: New.
include/opcode/
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (aarch64_op): Add OP_BFC.
opcodes/
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-asm.c (convert_bfc_to_bfm): New.
(convert_to_real): Add case for OP_BFC.
* aarch64-dis-2.c: Regenerate.
* aarch64-dis.c: (convert_bfm_to_bfc): New.
(convert_to_alias): Add case for OP_BFC.
* aarch64-opc-2.c: Regenerate.
* aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
to allow width operand in three-operand instructions.
* aarch64-tbl.h (QL_BF1): New.
(aarch64_feature_v8_2): New.
(ARMV8_2): New.
(aarch64_opcode_table): Add "bfc".
Change-Id: I6efe318b2538ba11f0caece7c6d70957441c872b
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 86bc029..ddfc577 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -236,6 +236,13 @@ QLF4(X,X,imm_0_63,imm_0_63), \ } +/* e.g. BFC <Wd>, #<immr>, #<imms>. */ +#define QL_BF1 \ +{ \ + QLF3 (W, imm_0_31, imm_1_32), \ + QLF3 (X, imm_0_63, imm_1_64), \ +} + /* e.g. UBFIZ <Wd>, <Wn>, #<lsb>, #<width>. */ #define QL_BF2 \ { \ @@ -1226,6 +1233,8 @@ static const aarch64_feature_set aarch64_feature_lor = AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0); static const aarch64_feature_set aarch64_feature_rdma = AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0); +static const aarch64_feature_set aarch64_feature_v8_2 = + AARCH64_FEATURE (AARCH64_FEATURE_V8_2, 0); #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -1235,6 +1244,7 @@ static const aarch64_feature_set aarch64_feature_rdma = #define LSE &aarch64_feature_lse #define LOR &aarch64_feature_lor #define RDMA &aarch64_feature_rdma +#define ARMV8_2 &aarch64_feature_v8_2 struct aarch64_opcode aarch64_opcode_table[] = { @@ -1777,6 +1787,8 @@ struct aarch64_opcode aarch64_opcode_table[] = {"asr", 0x13000000, 0x7f800000, bitfield, OP_ASR_IMM, CORE, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV}, {"bfm", 0x33000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N}, {"bfi", 0x33000000, 0x7f800000, bitfield, OP_BFI, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV}, + {"bfc", 0x330003e0, 0x7f8003e0, bitfield, OP_BFC, ARMV8_2, + OP3 (Rd, IMM, WIDTH), QL_BF1, F_ALIAS | F_P2 | F_CONV}, {"bfxil", 0x33000000, 0x7f800000, bitfield, OP_BFXIL, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV}, {"ubfm", 0x53000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N}, {"ubfiz", 0x53000000, 0x7f800000, bitfield, OP_UBFIZ, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV}, |