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| author | Matthew Wahab <matthew.wahab@arm.com> | 2015-12-14 17:40:03 +0000 |
|---|---|---|
| committer | Matthew Wahab <matthew.wahab@arm.com> | 2015-12-14 17:42:16 +0000 |
| commit | b5b0f34c669a91b9d873221ea3d688cf7f495ab5 (patch) | |
| tree | f9de996366ed0f1cf1d33b01222bfaf891f9f39b /opcodes/aarch64-tbl.h | |
| parent | b195470dd29e8a5c8810209fb2d22c30004fe6ab (diff) | |
| download | gdb-b5b0f34c669a91b9d873221ea3d688cf7f495ab5.zip gdb-b5b0f34c669a91b9d873221ea3d688cf7f495ab5.tar.gz gdb-b5b0f34c669a91b9d873221ea3d688cf7f495ab5.tar.bz2 | |
[AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch extends
instructions in the group Adv.SIMD Shift By Immediate to support FP16,
making this support available when +simd+fp16 is enabled.
The new instructions legal make some uses of the 4h vector type that had
been invalid. This patch adjusts a test that checks for these uses.
The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, #<imm>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes
instructions.
* gas/aarch64/illegal.d: Update expected output.
* gas/aarch64/illegal.s: Replace tests for illegal use of 'h'
specifier.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_VSHIFT_H): New.
(aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
and fcvtzu to the Adv.SIMD shift by immediate group.
Change-Id: I3480f63883d54db46562573185da6982f2365ee8
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index d00c3a0..9845caf 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -406,6 +406,13 @@ QLF3(V_2D , V_2D , V_2D ) \ } +/* e.g. SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */ +#define QL_VSHIFT_H \ +{ \ + QLF3 (V_4H, V_4H, V_4H), \ + QLF3 (V_8H, V_8H, V_8H) \ +} + /* e.g. SHRN<Q> <Vd>.<Tb>, <Vn>.<Ta>, #<shift>. */ #define QL_VSHIFTN \ { \ @@ -1838,7 +1845,11 @@ struct aarch64_opcode aarch64_opcode_table[] = {"sshll2", 0x4f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS}, {"sxtl2", 0x4f00a400, 0xff87fc00, asimdshf, OP_SXTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV}, {"scvtf", 0xf00e400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0}, + {"scvtf", 0xf10e400, 0xbf80fc00, asimdshf, 0, SIMD_F16, + OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0}, {"fcvtzs", 0xf00fc00, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0}, + {"fcvtzs", 0xf10fc00, 0xbf80fc00, asimdshf, 0, SIMD_F16, + OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0}, {"ushr", 0x2f000400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0}, {"usra", 0x2f001400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0}, {"urshr", 0x2f002400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0}, @@ -1860,7 +1871,11 @@ struct aarch64_opcode aarch64_opcode_table[] = {"ushll2", 0x6f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS}, {"uxtl2", 0x6f00a400, 0xff87fc00, asimdshf, OP_UXTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV}, {"ucvtf", 0x2f00e400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0}, + {"ucvtf", 0x2f10e400, 0xbf80fc00, asimdshf, 0, SIMD_F16, + OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0}, {"fcvtzu", 0x2f00fc00, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0}, + {"fcvtzu", 0x2f10fc00, 0xbf80fc00, asimdshf, 0, SIMD_F16, + OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0}, /* AdvSIMD TBL/TBX. */ {"tbl", 0xe000000, 0xbfe09c00, asimdtbl, 0, SIMD, OP3 (Vd, LVn, Vm), QL_TABLE, F_SIZEQ}, {"tbx", 0xe001000, 0xbfe09c00, asimdtbl, 0, SIMD, OP3 (Vd, LVn, Vm), QL_TABLE, F_SIZEQ}, |