diff options
| author | Victor Do Nascimento <victor.donascimento@arm.com> | 2023-11-15 17:21:39 +0000 |
|---|---|---|
| committer | Victor Do Nascimento <victor.donascimento@arm.com> | 2024-01-09 10:16:40 +0000 |
| commit | a9e2cefdf00202e0ba59825bd66a01ec41ac3ed0 (patch) | |
| tree | b62a75e4faa6bd99b6af833302c239d1457d2e74 /opcodes/aarch64-tbl.h | |
| parent | 92d8946670571118cccdbcd36d35300af33da4af (diff) | |
| download | gdb-a9e2cefdf00202e0ba59825bd66a01ec41ac3ed0.zip gdb-a9e2cefdf00202e0ba59825bd66a01ec41ac3ed0.tar.gz gdb-a9e2cefdf00202e0ba59825bd66a01ec41ac3ed0.tar.bz2 | |
aarch64: Implement TLBIP 128-bit instruction
The addition of 128-bit page table descriptors and, with it, the
addition of 128-bit system registers for these means that special
"invalidate translation table entry" instructions are needed to cope
with the new 128-bit model. This is introduced with the `tlbpi'
instruction, implemented here.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index ec14e4b..bb8f343 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -4218,6 +4218,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = CORE_INSN ("dc", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS), CORE_INSN ("ic", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)), CORE_INSN ("tlbi",0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)), + D128_INSN ("tlbip",0xd5480000, 0xfff80000, OP3 (SYSREG_TLBIP, Rt_SYS, PAIRREG_OR_XZR), QL_SRC_X2, F_ALIAS| F_OPD1_OPT | F_OPD_PAIR_OPT | F_DEFAULT (0x1f)), V8_7A_INSN ("wfet", 0xd5031000, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS), V8_7A_INSN ("wfit", 0xd5031020, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS), PREDRES_INSN ("cfp", 0xd50b7380, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS), @@ -6351,6 +6352,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = "an instruction cache maintenance operation specifier") \ Y(SYSTEM, sysins_op, "SYSREG_TLBI", 0, F(), \ "a TBL invalidation operation specifier") \ + Y(SYSTEM, sysins_op, "SYSREG_TLBIP", 0, F(), \ + "a 128-bit TBL invalidation operation specifier") \ Y(SYSTEM, sysins_op, "SYSREG_SR", 0, F(), \ "a Speculation Restriction option name (RCTX)") \ Y(SYSTEM, barrier, "BARRIER", 0, F(), \ |