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author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-07-08 17:44:24 +0100 |
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committer | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-07-08 17:45:54 +0100 |
commit | 984f5ebb7b54da4aefb26efd70caa01df98cdaf5 (patch) | |
tree | eeec3baa65f0dbdab13fe14b491ec5e556f1c830 /opcodes/aarch64-tbl.h | |
parent | 166da3c27916716d7bdb364528a9e79ca7c9ec28 (diff) | |
download | gdb-984f5ebb7b54da4aefb26efd70caa01df98cdaf5.zip gdb-984f5ebb7b54da4aefb26efd70caa01df98cdaf5.tar.gz gdb-984f5ebb7b54da4aefb26efd70caa01df98cdaf5.tar.bz2 |
aarch64: Add support for sve2p1 tblq instruction.
This patch adds support for SVE2p1 "tblq" instruction, spec is available here [1].
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
Diffstat (limited to 'opcodes/aarch64-tbl.h')
-rw-r--r-- | opcodes/aarch64-tbl.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 81b23b3..56a6c9d 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -6641,6 +6641,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0), SVE2p1_INSN("orqv",0x041c2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0), + SVE2p1_INSN("tblq",0x4400f800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm_16), OP_SVE_VVV_BHSD, F_OD(1), 0), SVE2p1_INSNC("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM4), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1), SVE2p1_INSN("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_QZD, F_OD (1), 0), |