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authorTamar Christina <tamar.christina@arm.com>2017-12-19 12:05:20 +0000
committerTamar Christina <tamar.christina@arm.com>2017-12-19 12:21:12 +0000
commit00c2093f698e8f40c04340cb1832d09e11ece237 (patch)
treeff7998cdf1ba5a074df429a9c830769477958a85 /opcodes/aarch64-tbl.h
parenta3b3345ae62503982698171bcfce0afe23bd8a31 (diff)
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Correct disassembly of dot product instructions.
Dot products deviate from the normal disassembly rules for lane indexed instruction. Their canonical representation is in the form of: v0.2s, v0.8b, v0.4b[0] instead of v0.2s, v0.8b, v0.b[0] to try to denote that these instructions select 4x 1 byte elements instead of a single 1 byte element. Previously we were disassembling them following the normal rules, this patch corrects the disassembly. gas/ PR gas/22559 * config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_S_4B. * gas/testsuite/gas/aarch64/dotproduct.d: Update disassembly. include/ PR gas/22559 * aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_S_4B. opcodes/ PR gas/22559 * aarch64-asm.c (aarch64_ins_reglane): Change AARCH64_OPND_QLF_S_B to AARCH64_OPND_QLF_S_4B * aarch64-dis.c (aarch64_ext_reglane): Change AARCH64_OPND_QLF_S_B to AARCH64_OPND_QLF_S_4B * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant. * aarch64-tbl.h (QL_V2DOT): Change S_B to S_4B.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
-rw-r--r--opcodes/aarch64-tbl.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 11587dc..e38ab20 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1992,8 +1992,8 @@
/* e.g. UDOT <Vd>.2S, <Vn>.8B, <Vm>.4B[<index>]. */
#define QL_V2DOT \
{ \
- QLF3(V_2S, V_8B, S_B),\
- QLF3(V_4S, V_16B, S_B),\
+ QLF3(V_2S, V_8B, S_4B),\
+ QLF3(V_4S, V_16B, S_4B),\
}
/* e.g. SHA512H <Qd>, <Qn>, <Vm>.2D . */