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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-01-15 09:38:39 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2024-01-15 11:45:41 +0000 |
| commit | b34104edab8bb399ade7a6c0865af47ff765d576 (patch) | |
| tree | 72362358b49d5fe57f67567748625008744344f9 /opcodes/aarch64-tbl.h | |
| parent | 39092c7a1fb0927fbbdb40e1142de816d6f3f097 (diff) | |
| download | gdb-b34104edab8bb399ade7a6c0865af47ff765d576.zip gdb-b34104edab8bb399ade7a6c0865af47ff765d576.tar.gz gdb-b34104edab8bb399ade7a6c0865af47ff765d576.tar.bz2 | |
PATCH 5/6][Binutils] aarch64: Add SVE2.1 fmin and fmax instructions.
Hi,
This patch add support for SVE2.1 instruction faddqv,
fmaxnmqv, fmaxqv, fminnmqv and fminqv.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 07f4eb3..f01ca2a 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1922,6 +1922,12 @@ QLF3(V_4S,NIL,S_S), \ QLF3(V_2D,NIL,S_D), \ } +#define OP_SVE_vUS_HSD_HSD \ +{ \ + QLF3(V_8H,NIL,S_H), \ + QLF3(V_4S,NIL,S_S), \ + QLF3(V_2D,NIL,S_D), \ +} #define OP_SVE_VMV_SD \ { \ QLF3(S_S,P_M,S_S), \ @@ -6339,6 +6345,12 @@ const struct aarch64_opcode aarch64_opcode_table[] = SVE2p1_INSNC("uminqv",0x040f2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0), SVE2p1_INSNC("eorqv",0x041d2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0), + SVE2p1_INSNC("faddqv",0x6410a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0), + SVE2p1_INSNC("fmaxnmqv",0x6414a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0), + SVE2p1_INSNC("fmaxqv",0x6416a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0), + SVE2p1_INSNC("fminnmqv",0x6415a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0), + SVE2p1_INSNC("fminqv",0x6417a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0), + SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index1, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0), SVE2p1_INSN("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zd, SVE_Zm_imm4), OP_SVE_BBB, 0, 0), |