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| author | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:22 +0100 |
|---|---|---|
| committer | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:22 +0100 |
| commit | 3c17238bc9fe8a078a6199470291f07bab9c64c8 (patch) | |
| tree | 31443cb03fc7932249004d085552ab29ab5a9556 /opcodes/aarch64-tbl.h | |
| parent | cd50a87ae29f163e7d254729a902a5e51fcccbbc (diff) | |
| download | gdb-3c17238bc9fe8a078a6199470291f07bab9c64c8.zip gdb-3c17238bc9fe8a078a6199470291f07bab9c64c8.tar.gz gdb-3c17238bc9fe8a078a6199470291f07bab9c64c8.tar.bz2 | |
[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.
Include a new iclass to extract the variant from the most significant 3
bits of this operand.
Instructions such as rshrnb include a constant shift amount as an
operand, where the most significant three bits of this operand determine
what size elements the instruction is operating on.
The new SVE_SHRIMM_UNPRED_22 operand denotes this constant encoded in
bits 22:20-19:18-16 while the new sve_shift_tsz_hsd iclass denotes that
the SVE qualifier is encoded in bits 22:20-19.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22
operand.
(enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-asm.c (aarch64_ins_sve_shrimm):
(aarch64_encode_variant_using_iclass): Handle
sve_shift_tsz_hsd iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_shift_tsz_hsd iclass decode.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_SHRIMM_UNPRED_22.
(aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
operand.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index ba5d6b5..6f8f47a 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -4923,10 +4923,13 @@ struct aarch64_opcode aarch64_opcode_table[] = F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-left immediate operand") \ Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_UNPRED", 0, \ F(FLD_SVE_tszh,FLD_imm5), "a shift-left immediate operand") \ - Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_PRED", 0, \ + Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_PRED", 1 << OPD_F_OD_LSB, \ F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-right immediate operand") \ - Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_UNPRED", 0, \ + Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_UNPRED", 1 << OPD_F_OD_LSB, \ F(FLD_SVE_tszh,FLD_imm5), "a shift-right immediate operand") \ + Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_UNPRED_22", 2 << OPD_F_OD_LSB, \ + F(FLD_SVE_sz, FLD_SVE_tszl_19, FLD_SVE_imm3), \ + "a shift-right immediate operand") \ Y(IMMEDIATE, imm, "SVE_SIMM5", OPD_F_SEXT, F(FLD_SVE_imm5), \ "a 5-bit signed immediate") \ Y(IMMEDIATE, imm, "SVE_SIMM5B", OPD_F_SEXT, F(FLD_SVE_imm5b), \ |