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| author | Richard Sandiford <richard.sandiford@arm.com> | 2017-02-24 18:27:26 +0000 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2017-02-24 18:27:26 +0000 |
| commit | f482d3044722558c3b16f54b33b0855bfbae36b1 (patch) | |
| tree | 7daa88fa21eaed9bb36de3a5df2b4ded773e50b8 /opcodes/aarch64-tbl.h | |
| parent | 6b4bf3bc355bea57be3c0f6f61008a23b9067a11 (diff) | |
| download | gdb-f482d3044722558c3b16f54b33b0855bfbae36b1.zip gdb-f482d3044722558c3b16f54b33b0855bfbae36b1.tar.gz gdb-f482d3044722558c3b16f54b33b0855bfbae36b1.tar.bz2 | |
[AArch64] Add a "compnum" feature
This patch adds a named "compnum" feature for the ARMv8.3-A FCADD
and FCMLA extensions.
include/
* opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro.
(AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM.
opcodes/
* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
(aarch64_feature_compnum): ...this.
(SIMD_V8_3): Replace with...
(COMPNUM): ...this.
(CNUM_INSN): New macro.
(aarch64_opcode_table): Use it for the complex number instructions.
gas/
* doc/c-aarch64.texi: Add a "compnum" entry.
* config/tc-aarch64.c (aarch64_features): Likewise,
* testsuite/gas/aarch64/advsimd-compnum.s: New test.
* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 472205f..705ace6 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1938,8 +1938,8 @@ static const aarch64_feature_set aarch64_feature_v8_3 = AARCH64_FEATURE (AARCH64_FEATURE_V8_3, 0); static const aarch64_feature_set aarch64_feature_fp_v8_3 = AARCH64_FEATURE (AARCH64_FEATURE_V8_3 | AARCH64_FEATURE_FP, 0); -static const aarch64_feature_set aarch64_feature_simd_v8_3 = - AARCH64_FEATURE (AARCH64_FEATURE_V8_3 | AARCH64_FEATURE_SIMD, 0); +static const aarch64_feature_set aarch64_feature_compnum = + AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM, 0); static const aarch64_feature_set aarch64_feature_rcpc = AARCH64_FEATURE (AARCH64_FEATURE_RCPC, 0); @@ -1959,7 +1959,7 @@ static const aarch64_feature_set aarch64_feature_rcpc = #define SVE &aarch64_feature_sve #define ARMV8_3 &aarch64_feature_v8_3 #define FP_V8_3 &aarch64_feature_fp_v8_3 -#define SIMD_V8_3 &aarch64_feature_simd_v8_3 +#define COMPNUM &aarch64_feature_compnum #define RCPC &aarch64_feature_rcpc #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ @@ -1989,6 +1989,8 @@ static const aarch64_feature_set aarch64_feature_rcpc = FLAGS | F_STRICT, TIED, NULL } #define V8_3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, ARMV8_3, OPS, QUALS, FLAGS, 0, NULL } +#define CNUM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, OP, COMPNUM, OPS, QUALS, FLAGS, 0, NULL } #define RCPC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, RCPC, OPS, QUALS, FLAGS, 0, NULL } @@ -2130,7 +2132,7 @@ struct aarch64_opcode aarch64_opcode_table[] = SF16_INSN ("fmulx", 0x2f009000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ), RDMA_INSN ("sqrdmlah",0x2f00d000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), RDMA_INSN ("sqrdmlsh",0x2f00f000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), - {"fcmla", 0x2f001000, 0xbf009400, asimdelem, OP_FCMLA_ELEM, SIMD_V8_3, OP4 (Vd, Vn, Em, IMM_ROT2), QL_ELEMENT_ROT, F_SIZEQ, 0, NULL}, + CNUM_INSN ("fcmla", 0x2f001000, 0xbf009400, asimdelem, OP_FCMLA_ELEM, OP4 (Vd, Vn, Em, IMM_ROT2), QL_ELEMENT_ROT, F_SIZEQ), /* AdvSIMD EXT. */ SIMD_INSN ("ext", 0x2e000000, 0xbfe08400, asimdext, 0, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ), /* AdvSIMD modified immediate. */ @@ -2374,8 +2376,8 @@ struct aarch64_opcode aarch64_opcode_table[] = /* AdvSIMD three same extension. */ RDMA_INSN ("sqrdmlah",0x2e008400, 0xbf20fe00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), RDMA_INSN ("sqrdmlsh",0x2e008c00, 0xbf20fe00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), - {"fcmla", 0x2e00c400, 0xbf20e400, asimdsame, 0, SIMD_V8_3, OP4 (Vd, Vn, Vm, IMM_ROT1), QL_V3SAMEHSD_ROT, F_SIZEQ, 0, NULL}, - {"fcadd", 0x2e00e400, 0xbf20ec00, asimdsame, 0, SIMD_V8_3, OP4 (Vd, Vn, Vm, IMM_ROT3), QL_V3SAMEHSD_ROT, F_SIZEQ, 0, NULL}, + CNUM_INSN ("fcmla", 0x2e00c400, 0xbf20e400, asimdsame, 0, OP4 (Vd, Vn, Vm, IMM_ROT1), QL_V3SAMEHSD_ROT, F_SIZEQ), + CNUM_INSN ("fcadd", 0x2e00e400, 0xbf20ec00, asimdsame, 0, OP4 (Vd, Vn, Vm, IMM_ROT3), QL_V3SAMEHSD_ROT, F_SIZEQ), /* AdvSIMD shift by immediate. */ SIMD_INSN ("sshr", 0xf000400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), SIMD_INSN ("ssra", 0xf001400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), |