aarch64: Add maximum immediate value to aarch64_sys_reg

The immediate form of MSR has a 4-bit immediate field (in CRm).
However, many forms of MSR require a smaller immediate.  These cases
are identified by value in operand_general_constraint_met_p,
but they're now the common case rather than the exception.

This patch therefore adds the maximum value to the sys_reg
description and gets the range from there.  It also enforces
the minimum of 0, which avoids a situation in which:

  msr dit, #2

would give the expected:

  Error: immediate value out of range 0 to 1

whereas:

  msr dit, #-1

would give:

  Error: immediate value out of range 0 to 15

(from the later UIMM4 checking).

Also:

- we were reporting the first error above against the wrong operand
- TCO takes a single-bit immediate, but we previously allowed
  all 16 values.
  [https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions/MSR--immediate---Move-immediate-value-to-Special-Register-?lang=en]

opcodes/
	* aarch64-opc.h (F_REG_MAX_VALUE, F_GET_REG_MAX_VALUE): New macros.
	* aarch64-opc.c (operand_general_constraint_met_p): Read the
	maximum MSR immediate value from aarch64_pstatefields.
	(aarch64_pstatefields): Add the maximum immediate value
	for each register.

gas/
	* testsuite/gas/aarch64/sysreg-4.s: Use an immediate value of 1
	rather than 8 for the TCO test.
	* testsuite/gas/aarch64/sysreg-4.d: Update accordingly.
	* testsuite/gas/aarch64/armv8_2-a-illegal.l: Fix operand number
	in MSR immediate error messages.
	* testsuite/gas/aarch64/diagnostic.l: Likewise.
	* testsuite/gas/aarch64/pan-illegal.l: Likewise.
	* testsuite/gas/aarch64/ssbs-illegal1.l: Likewise.
	* testsuite/gas/aarch64/illegal-sysreg-4b.s,
	* testsuite/gas/aarch64/illegal-sysreg-4b.d,
	* testsuite/gas/aarch64/illegal-sysreg-4b.l: New test.

1 files changed, 4 insertions, 0 deletions

diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 49f3013..c7599fb 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -273,6 +273,10 @@ verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
         (F_REG_IN_CRM | PSTATE_ENCODE_CRM(CVAL) \
          | F_IMM_IN_CRM | PSTATE_ENCODE_CRM_IMM(IMASK))
 
+/* Bits [15, 18] contain the maximum value for an immediate MSR.  */
+#define F_REG_MAX_VALUE(X) ((X) << 15)
+#define F_GET_REG_MAX_VALUE(X) (((X) >> 15) & 0x0f)
+
 /* HINT operand flags.  */
 #define HINT_OPD_F_NOPRINT	(1 << 0)  /* Should not be printed.  */