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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2022-11-14 16:47:22 +0000 |
|---|---|---|
| committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2022-11-14 16:47:22 +0000 |
| commit | 1f7b42d52a8cb690c259eaa4975a608e82d7267a (patch) | |
| tree | 8e0d1faeeb5f8cfb1cf2caf218936c625ac46e98 /opcodes/aarch64-opc.c | |
| parent | 255571cdbf05213cc96feefb779c4158df453398 (diff) | |
| download | gdb-1f7b42d52a8cb690c259eaa4975a608e82d7267a.zip gdb-1f7b42d52a8cb690c259eaa4975a608e82d7267a.tar.gz gdb-1f7b42d52a8cb690c259eaa4975a608e82d7267a.tar.bz2 | |
aarch64: Add support for Common Short Sequence Compression extension
This patch adds support for the CSSC extension and its corresponding
instructions: ABS, CNT, CTZ, SMAX, UMAX, SMIN, UMIN.
gas/ChangeLog:
* config/tc-aarch64.c (parse_operands): Handle new operand types.
* doc/c-aarch64.texi: Document new extension.
* testsuite/gas/aarch64/cssc.d: New test.
* testsuite/gas/aarch64/cssc.s: New test.
include/ChangeLog:
* opcode/aarch64.h (AARCH64_FEATURE_CSSC): New feature Macro.
(enum aarch64_opnd): New operand types.
(enum aarch64_insn_class): New instruction class.
opcodes/ChangeLog:
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-opc.c (operand_general_constraint_met_p): Update for new
operand types.
(aarch64_print_operand): Likewise.
* aarch64-opc.h (enum aarch64_field_kind): Declare FLD_CSSC_imm8 field.
* aarch64-tbl.h (aarch64_feature_cssc): Define new feature set.
(CSSC): Define new feature set Macro.
(CSSC_INSN): Define new instruction type.
(aarch64_opcode_table): Add new instructions.
Diffstat (limited to 'opcodes/aarch64-opc.c')
| -rw-r--r-- | opcodes/aarch64-opc.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index a2882bd..dd888b3 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -342,6 +342,7 @@ const aarch64_field fields[] = { 12, 2 }, /* SM3: Indexed element SM3 2 bits index immediate. */ { 22, 1 }, /* sz: 1-bit element size select. */ { 10, 2 }, /* CRm_dsb_nxs: 2-bit imm. encoded in CRm<3:2>. */ + { 10, 8 }, /* CSSC_imm8. */ }; enum aarch64_operand_class @@ -2176,6 +2177,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_SVE_UIMM7: case AARCH64_OPND_SVE_UIMM8: case AARCH64_OPND_SVE_UIMM8_53: + case AARCH64_OPND_CSSC_UIMM8: size = get_operand_fields_width (get_operand_from_code (type)); assert (size < 32); if (!value_fit_unsigned_field_p (opnd->imm.value, size)) @@ -2206,6 +2208,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_SVE_SIMM5B: case AARCH64_OPND_SVE_SIMM6: case AARCH64_OPND_SVE_SIMM8: + case AARCH64_OPND_CSSC_SIMM8: size = get_operand_fields_width (get_operand_from_code (type)); assert (size < 32); if (!value_fit_signed_field_p (opnd->imm.value, size)) @@ -3620,6 +3623,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SVE_IMM_ROT1: case AARCH64_OPND_SVE_IMM_ROT2: case AARCH64_OPND_SVE_IMM_ROT3: + case AARCH64_OPND_CSSC_SIMM8: + case AARCH64_OPND_CSSC_UIMM8: snprintf (buf, size, "%s", style_imm (styler, "#%" PRIi64, opnd->imm.value)); break; |