diff options
| author | Jiong Wang <jiong.wang@arm.com> | 2014-09-03 14:40:41 +0100 |
|---|---|---|
| committer | Jiong Wang <jiong.wang@arm.com> | 2014-09-03 14:53:53 +0100 |
| commit | ee804238f097e91088a340c15891170f2748b4fd (patch) | |
| tree | 22d92253b206d824681e73039fe861f8d20ec8df /opcodes/aarch64-opc.c | |
| parent | 97ea6506c45ab5519483a0221fdc049038496492 (diff) | |
| download | gdb-ee804238f097e91088a340c15891170f2748b4fd.zip gdb-ee804238f097e91088a340c15891170f2748b4fd.tar.gz gdb-ee804238f097e91088a340c15891170f2748b4fd.tar.bz2 | |
[PATCH/AArch64] Implement LSE feature
2014-09-03 Jiong Wang <jiong.wang@arm.com>
gas/
* config/tc-aarch64.c (parse_operands): Recognize PAIRREG.
(aarch64_features): Add entry for lse extension.
include/opcode/
* aarch64.h (AARCH64_FEATURE_LSE): New feature added.
(aarch64_opnd): Add AARCH64_OPND_PAIRREG.
(aarch64_insn_class): Add lse_atomic.
(F_LSE_SZ): New field added.
(opcode_has_special_coder): Recognize F_LSE_SZ.
opcode/
* aarch64-tbl.h (QL_R4NIL): New qualifiers.
(aarch64_feature_lse): New feature added.
(LSE): New Added.
(aarch64_opcode_table): New LSE instructions added. Improve
descriptions for ldarb/ldarh/ldar.
(aarch64_opcode_table): Describe PAIRREG.
* aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
* aarch64-opc.c (fields): Add entry for F_LSE_SZ.
(aarch64_print_operand): Recognize PAIRREG.
(operand_general_constraint_met_p): Check reg pair constraints for CASP
instructions.
* aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
(do_special_decoding): Recognize F_LSE_SZ.
* aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
gas/testsuite/
* gas/aarch64/lse-atomic.d: New.
* gas/aarch64/lse-atomic.s: Likewise.
* gas/aarch64/illegal-lse.d: Likewise.
* gas/aarch64/illegal-lse.l: Likewise.
* gas/aarch64/illegal-lse.s: Likewise.
* gas/aarch64/diagnostic.s: Check processor feature detect for lse
instruction.
* gas/aarch64/diagnostic.l: Likewise.
Diffstat (limited to 'opcodes/aarch64-opc.c')
| -rw-r--r-- | opcodes/aarch64-opc.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index be01ab3..430cf5b 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -192,6 +192,7 @@ const aarch64_field fields[] = { 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */ { 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */ { 31, 1 }, /* sf: in integer data processing instructions. */ + { 30, 1 }, /* lse_size: in LSE extension atomic instructions. */ { 11, 1 }, /* H: in advsimd scalar x indexed element instructions. */ { 21, 1 }, /* L: in advsimd scalar x indexed element instructions. */ { 20, 1 }, /* M: in advsimd scalar x indexed element instructions. */ @@ -1254,6 +1255,25 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, switch (aarch64_operands[type].op_class) { case AARCH64_OPND_CLASS_INT_REG: + /* Check pair reg constraints for cas* instructions. */ + if (type == AARCH64_OPND_PAIRREG) + { + assert (idx == 1 || idx == 3); + if (opnds[idx - 1].reg.regno % 2 != 0) + { + set_syntax_error (mismatch_detail, idx - 1, + _("reg pair must start from even reg")); + return 0; + } + if (opnds[idx].reg.regno != opnds[idx - 1].reg.regno + 1) + { + set_syntax_error (mismatch_detail, idx, + _("reg pair must be contiguous")); + return 0; + } + break; + } + /* <Xt> may be optional in some IC and TLBI instructions. */ if (type == AARCH64_OPND_Rt_SYS) { @@ -2327,6 +2347,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_Rs: case AARCH64_OPND_Ra: case AARCH64_OPND_Rt_SYS: + case AARCH64_OPND_PAIRREG: /* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by the <ic_op>, therefore we we use opnd->present to override the generic optional-ness information. */ |