[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructions

This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order)

This patch adds the prediction restriction instructions (that is, cfp,
dvp, cpp). These instructions are retrospectively made optional for
all versions of the architecture from ARMv8.0 to ARMv8.4 and is
mandatory from ARMv8.5. Hence adding a new +predres which can be used
by the older architectures.

*** include/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_PREDRES): New.
	(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_PREDRES by default.
	(aarch64_opnd): Add AARCH64_OPND_SYSREG_SR.
	(aarch64_sys_regs_sr): Declare new table.

*** opcodes/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-dis.c (aarch64_ext_sysins_op): Add case for
	AARCH64_OPND_SYSREG_SR.
	* aarch64-opc.c (aarch64_print_operand): Likewise.
	(aarch64_sys_regs_sr): Define table.
	(aarch64_sys_ins_reg_supported_p): Check for RCTX with
	AARCH64_FEATURE_PREDRES.
	* aarch64-tbl.h (aarch64_feature_predres): New.
	(PREDRES, PREDRES_INSN): New.
	(aarch64_opcode_table): Add entries for cfp, dvp and cpp.
	(AARCH64_OPERANDS): Add new description for SYSREG_SR.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

*** gas/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (aarch64_sys_regs_sr_hsh): New.
	(parse_operands): Add entry for AARCH64_OPND_SYSREG_SR.
	(md_begin): Allocate and initialize aarch64_sys_regs_sr_hsh
	with aarch64_sys_regs_sr.
	(aarch64_features): Add new "predres" option for older
	architectures.
	* doc/c-aarch64.texi: Document the same.
	* testsuite/gas/aarch64/sysreg-4.s: New.
	* testsuite/gas/aarch64/sysreg-4.d: New.
	* testsuite/gas/aarch64/illegal-sysreg-4.d: New.
	* testsuite/gas/aarch64/illegal-sysreg-4.l: New.
	* testsuite/gas/aarch64/predres.s: New.
	* testsuite/gas/aarch64/predres.d: New.

1 files changed, 17 insertions, 0 deletions

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index ed75a9a..f3c436c 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -3630,6 +3630,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
     case AARCH64_OPND_SYSREG_DC:
     case AARCH64_OPND_SYSREG_IC:
     case AARCH64_OPND_SYSREG_TLBI:
+    case AARCH64_OPND_SYSREG_SR:
       snprintf (buf, size, "%s", opnd->sysins_op->name);
       break;
 
@@ -4458,6 +4459,17 @@ const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
     { 0,       CPENS(0,0,0,0), 0 }
 };
 
+const aarch64_sys_ins_reg aarch64_sys_regs_sr[] =
+{
+    /* RCTX is somewhat unique in a way that it has different values
+       (op2) based on the instruction in which it is used (cfp/dvp/cpp).
+       Thus op2 is masked out and instead encoded directly in the
+       aarch64_opcode_table entries for the respective instructions.  */
+    { "rctx",   CPENS(3,C7,C3,0), F_HASXT | F_ARCHEXT | F_REG_WRITE}, /* WO */
+
+    { 0,       CPENS(0,0,0,0), 0 }
+};
+
 bfd_boolean
 aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
 {
@@ -4482,6 +4494,11 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
     return FALSE;
 
+  /* CFP/DVP/CPP RCTX : Value are from aarch64_sys_regs_sr. */
+  if (reg->value == CPENS (3, C7, C3, 0)
+      && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PREDRES))
+    return FALSE;
+
   return TRUE;
 }