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| author | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:18 +0100 |
|---|---|---|
| committer | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:18 +0100 |
| commit | c469c86473273e115b267a6f8c93c8942deb93c4 (patch) | |
| tree | 287fc69d0de95ceb865fef1bb99c4e1bd85b7ef8 /opcodes/aarch64-opc.c | |
| parent | 116adc27470ed3682b6236e44e3b18838673036c (diff) | |
| download | gdb-c469c86473273e115b267a6f8c93c8942deb93c4.zip gdb-c469c86473273e115b267a6f8c93c8942deb93c4.tar.gz gdb-c469c86473273e115b267a6f8c93c8942deb93c4.tar.bz2 | |
[binutils][aarch64] New SVE_ADDR_ZX operand.
Add AARCH64_OPND_SVE_ADDR_ZX operand that allows a vector of addresses
in a Zn register, offset by an Xm register.
This is used with scatter/gather SVE2 instructions.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (REG_ZR): Macro specifying zero register.
(parse_address_main): Account for new addressing mode [Zn.S, Xm].
(parse_operands): Handle new SVE_ADDR_ZX operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_ADDR_ZX.
(aarch64_print_operand): Add printing for SVE_ADDR_ZX.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
Diffstat (limited to 'opcodes/aarch64-opc.c')
| -rw-r--r-- | opcodes/aarch64-opc.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 538d57e..23b1503 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -1899,6 +1899,17 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, max_value = 7; goto sve_imm_offset; + case AARCH64_OPND_SVE_ADDR_ZX: + /* Everything is already ensured by parse_operands or + aarch64_ext_sve_addr_rr_lsl (because this is a very specific + argument type). */ + assert (opnd->addr.offset.is_reg); + assert (opnd->addr.preind); + assert ((aarch64_operands[type].flags & OPD_F_NO_ZR) == 0); + assert (opnd->shifter.kind == AARCH64_MOD_LSL); + assert (opnd->shifter.operator_present == 0); + break; + case AARCH64_OPND_SVE_ADDR_R: case AARCH64_OPND_SVE_ADDR_RR: case AARCH64_OPND_SVE_ADDR_RR_LSL1: @@ -3583,6 +3594,13 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, get_offset_int_reg_name (opnd)); break; + case AARCH64_OPND_SVE_ADDR_ZX: + print_register_offset_address + (buf, size, opnd, + get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier), + get_64bit_int_reg_name (opnd->addr.offset.regno, 0)); + break; + case AARCH64_OPND_SVE_ADDR_RZ: case AARCH64_OPND_SVE_ADDR_RZ_LSL1: case AARCH64_OPND_SVE_ADDR_RZ_LSL2: |