aarch64: Add support for +mops

This patch adds support for FEAT_MOPS, an Armv8.8-A extension
that provides memcpy and memset acceleration instructions.

I took the perhaps controversial decision to generate the individual
instruction forms using macros rather than list them out individually.
This becomes useful with a follow-on patch to check that code follows
the correct P/M/E sequence.
[https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions?lang=en]

include/
	* opcode/aarch64.h (AARCH64_FEATURE_MOPS): New macro.
	(AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_MOPS.
	(AARCH64_OPND_MOPS_ADDR_Rd): New aarch64_opnd.
	(AARCH64_OPND_MOPS_ADDR_Rs): Likewise.
	(AARCH64_OPND_MOPS_WB_Rn): Likewise.

opcodes/
	* aarch64-asm.h (ins_x0_to_x30): New inserter.
	* aarch64-asm.c (aarch64_ins_x0_to_x30): New function.
	* aarch64-dis.h (ext_x0_to_x30): New extractor.
	* aarch64-dis.c (aarch64_ext_x0_to_x30): New function.
	* aarch64-tbl.h (aarch64_feature_mops): New feature set.
	(aarch64_feature_mops_memtag): Likewise.
	(MOPS, MOPS_MEMTAG, MOPS_INSN, MOPS_MEMTAG_INSN)
	(MOPS_CPY_OP1_OP2_PME_INSN, MOPS_CPY_OP1_OP2_INSN, MOPS_CPY_OP1_INSN)
	(MOPS_CPY_INSN, MOPS_SET_OP1_OP2_PME_INSN, MOPS_SET_OP1_OP2_INSN)
	(MOPS_SET_INSN): New macros.
	(aarch64_opcode_table): Add MOPS instructions.
	(aarch64_opcode_table): Add entries for AARCH64_OPND_MOPS_ADDR_Rd,
	AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn.
	* aarch64-opc.c (aarch64_print_operand): Handle
	AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and
	AARCH64_OPND_MOPS_WB_Rn.
	(verify_three_different_regs): New function.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.

gas/
	* doc/c-aarch64.texi: Document +mops.
	* config/tc-aarch64.c (parse_x0_to_x30): New function.
	(parse_operands): Handle AARCH64_OPND_MOPS_ADDR_Rd,
	AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn.
	(aarch64_features): Add "mops".
	* testsuite/gas/aarch64/mops.s, testsuite/gas/aarch64/mops.d: New test.
	* testsuite/gas/aarch64/mops_invalid.s,
	* testsuite/gas/aarch64/mops_invalid.d,
	* testsuite/gas/aarch64/mops_invalid.l: Likewise.

1 files changed, 41 insertions, 0 deletions

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index a77070e..cfd4781 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -3921,6 +3921,17 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
 	snprintf (buf, size, "%s", opnd->hint_option->name);
       break;
 
+    case AARCH64_OPND_MOPS_ADDR_Rd:
+    case AARCH64_OPND_MOPS_ADDR_Rs:
+      snprintf (buf, size, "[%s]!",
+		get_int_reg_name (opnd->reg.regno, AARCH64_OPND_QLF_X, 0));
+      break;
+
+    case AARCH64_OPND_MOPS_WB_Rn:
+      snprintf (buf, size, "%s!",
+		get_int_reg_name (opnd->reg.regno, AARCH64_OPND_QLF_X, 0));
+      break;
+
     default:
       snprintf (buf, size, "<invalid>");
       break;
@@ -5409,6 +5420,36 @@ verify_elem_sd (const struct aarch64_inst *inst, const aarch64_insn insn,
   return ERR_OK;
 }
 
+/* Check an instruction that takes three register operands and that
+   requires the register numbers to be distinct from one another.  */
+
+static enum err_type
+verify_three_different_regs (const struct aarch64_inst *inst,
+			     const aarch64_insn insn ATTRIBUTE_UNUSED,
+			     bfd_vma pc ATTRIBUTE_UNUSED,
+			     bool encoding ATTRIBUTE_UNUSED,
+			     aarch64_operand_error *mismatch_detail
+			       ATTRIBUTE_UNUSED,
+			     aarch64_instr_sequence *insn_sequence
+			       ATTRIBUTE_UNUSED)
+{
+  int rd, rs, rn;
+
+  rd = inst->operands[0].reg.regno;
+  rs = inst->operands[1].reg.regno;
+  rn = inst->operands[2].reg.regno;
+  if (rd == rs || rd == rn || rs == rn)
+    {
+      mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
+      mismatch_detail->error
+	= _("the three register operands must be distinct from one another");
+      mismatch_detail->index = -1;
+      return ERR_UND;
+    }
+
+  return ERR_OK;
+}
+
 /* Add INST to the end of INSN_SEQUENCE.  */
 
 static void