diff options
| author | Matthew Wahab <matthew.wahab@arm.com> | 2015-12-10 16:38:44 +0000 |
|---|---|---|
| committer | Matthew Wahab <matthew.wahab@arm.com> | 2015-12-10 16:40:45 +0000 |
| commit | d6bf7ce6c26cd31fe744419269dea999a3faaf8c (patch) | |
| tree | fe3bd85148f9052f67f022ce3459aea363295b9c /opcodes/aarch64-opc.c | |
| parent | ea2deeec92695c33045d71ffa73add6305b17b9a (diff) | |
| download | gdb-d6bf7ce6c26cd31fe744419269dea999a3faaf8c.zip gdb-d6bf7ce6c26cd31fe744419269dea999a3faaf8c.tar.gz gdb-d6bf7ce6c26cd31fe744419269dea999a3faaf8c.tar.bz2 | |
[AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction.
ARMv8.2 adds the new system instruction DC CVAP. This patch adds support
for the instruction to binutils, enabled when -march=armv8.2-a is
selected.
gas/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (parse_sys_ins_reg): Add check of
architectural support for system register.
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/sysreg-2.d: Add tests for dc instruction.
* gas/aarch64/sysreg-2.s: Add uses of dc instruction.
include/opcode/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
(aarch64_sys_ins_reg_supported_p): New.
Change-Id: I3158b97d9bbee9644c2d0e2986db807412ef1053
Diffstat (limited to 'opcodes/aarch64-opc.c')
| -rw-r--r-- | opcodes/aarch64-opc.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 2ae2f10..86aeae0 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -3264,6 +3264,7 @@ const aarch64_sys_ins_reg aarch64_sys_regs_dc[] = { "cvac", CPENS (3, C7, C10, 1), F_HASXT }, { "csw", CPENS (0, C7, C10, 2), F_HASXT }, { "cvau", CPENS (3, C7, C11, 1), F_HASXT }, + { "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT }, { "civac", CPENS (3, C7, C14, 1), F_HASXT }, { "cisw", CPENS (0, C7, C14, 2), F_HASXT }, { 0, CPENS(0,0,0,0), 0 } @@ -3329,6 +3330,21 @@ aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg) return (sys_ins_reg->flags & F_HASXT) != 0; } +extern bfd_boolean +aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features, + const aarch64_sys_ins_reg *reg) +{ + if (!(reg->flags & F_ARCHEXT)) + return TRUE; + + /* DC CVAP. Values are from aarch64_sys_regs_dc. */ + if (reg->value == CPENS (3, C7, C12, 1) + && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2)) + return FALSE; + + return TRUE; +} + #undef C0 #undef C1 #undef C2 |