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| author | Sudakshina Das <sudi.das@arm.com> | 2018-09-26 10:57:16 +0100 |
|---|---|---|
| committer | Richard Earnshaw <Richard.Earnshaw@arm.com> | 2018-10-09 15:39:29 +0100 |
| commit | af4bcb4ce6939da1738c847a06789d2223b67ca4 (patch) | |
| tree | c97aeb157e74b8884981ab2852c2b3ec38e1756b /opcodes/aarch64-opc.c | |
| parent | 3fd229a447cd28a70bfd921f617bc6c3553b8fdd (diff) | |
| download | gdb-af4bcb4ce6939da1738c847a06789d2223b67ca4.zip gdb-af4bcb4ce6939da1738c847a06789d2223b67ca4.tar.gz gdb-af4bcb4ce6939da1738c847a06789d2223b67ca4.tar.bz2 | |
[PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructions
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.
This patch adds the following:
MSR Xn, RNDR
MSR Xn, RNDRRS
These are optional instructions in ARMv8.5-A and hence the new
+rng is added.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_RNG): New.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs): New entries for
rndr and rndrrs.
(aarch64_sys_reg_supported_p): New check for above.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_features): New "rng" option.
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/sysreg-4.s: Test both instructions.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
Diffstat (limited to 'opcodes/aarch64-opc.c')
| -rw-r--r-- | opcodes/aarch64-opc.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 9562ba8..8d96392 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -3855,6 +3855,8 @@ const aarch64_sys_reg aarch64_sys_regs [] = { "contextidr_el1", CPENC(3,0,C13,C0,1), 0 }, { "contextidr_el2", CPENC (3, 4, C13, C0, 1), F_ARCHEXT }, { "contextidr_el12", CPENC (3, 5, C13, C0, 1), F_ARCHEXT }, + { "rndr", CPENC(3,3,C2,C4,0), F_ARCHEXT | F_REG_READ }, /* RO */ + { "rndrrs", CPENC(3,3,C2,C4,1), F_ARCHEXT | F_REG_READ }, /* RO */ { "tpidr_el0", CPENC(3,3,C13,C0,2), 0 }, { "tpidrro_el0", CPENC(3,3,C13,C0,3), 0 }, /* RW */ { "tpidr_el1", CPENC(3,0,C13,C0,4), 0 }, @@ -4286,6 +4288,14 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features, && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4)) return FALSE; + /* Random Number Instructions. For now they are available + (and optional) only with ARMv8.5-A. */ + if ((reg->value == CPENC (3, 3, C2, C4, 0) + || reg->value == CPENC (3, 3, C2, C4, 1)) + && !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RNG) + && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_5))) + return FALSE; + return TRUE; } |