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| author | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:17 +0100 |
|---|---|---|
| committer | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:17 +0100 |
| commit | 116adc27470ed3682b6236e44e3b18838673036c (patch) | |
| tree | f3d401952aff1a968fb8466cb38b2b6a6d00500d /opcodes/aarch64-opc.c | |
| parent | 3bd82c86f0f432bd7653101069bf056fda14b7cd (diff) | |
| download | gdb-116adc27470ed3682b6236e44e3b18838673036c.zip gdb-116adc27470ed3682b6236e44e3b18838673036c.tar.gz gdb-116adc27470ed3682b6236e44e3b18838673036c.tar.bz2 | |
[binutils][aarch64] New SVE_Zm3_11_INDEX operand.
Introduce new operand SVE_Zm3_11_INDEX that indicates a register between
z0-z7 stored in bits 18-16 and an index stored in bits 20-19:11.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm3_11_INDEX
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_Zm3_11_INDEX.
(aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
(fields): Handle SVE_i3l and SVE_i3h2 fields.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
fields.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
Diffstat (limited to 'opcodes/aarch64-opc.c')
| -rw-r--r-- | opcodes/aarch64-opc.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 97cbfc8..538d57e 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -294,6 +294,8 @@ const aarch64_field fields[] = { 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */ { 5, 1 }, /* SVE_i1: single-bit immediate. */ { 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */ + { 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */ + { 19, 2 }, /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19]. */ { 16, 3 }, /* SVE_imm3: 3-bit immediate field. */ { 16, 4 }, /* SVE_imm4: 4-bit immediate field. */ { 5, 5 }, /* SVE_imm5: 5-bit immediate field. */ @@ -1515,6 +1517,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, { case AARCH64_OPND_SVE_Zm3_INDEX: case AARCH64_OPND_SVE_Zm3_22_INDEX: + case AARCH64_OPND_SVE_Zm3_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: size = get_operand_fields_width (get_operand_from_code (type)); shift = get_operand_specific_data (&aarch64_operands[type]); @@ -3303,6 +3306,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SVE_Zm3_INDEX: case AARCH64_OPND_SVE_Zm3_22_INDEX: + case AARCH64_OPND_SVE_Zm3_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: case AARCH64_OPND_SVE_Zn_INDEX: snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno, |