AArch64: add GAS support for UDF instruction

binutils * testsuite/binutils-all/aarch64/in-order-all.d: Update to use new
          disassembly.
        * testsuite/binutils-all/aarch64/out-of-order-all.d: Likewise.

ld/     * testsuite/ld-aarch64/erratum843419_tls_ie.d: Use udf in disassembly.
        * testsuite/ld-aarch64/farcall-b-section.d: Likewise.
        * testsuite/ld-aarch64/farcall-back.d: Likewise.
        * testsuite/ld-aarch64/farcall-bl-section.d: Likewise.

gas/   * config/tc-aarch64.c (fix_insn): Implement for AARCH64_OPND_UNDEFINED.
          (parse_operands): Implement for AARCH64_OPND_UNDEFINED.
        * testsuite/gas/aarch64/udf.s: New.
        * testsuite/gas/aarch64/udf.d: New.
        * testsuite/gas/aarch64/udf-invalid.s: New.
        * testsuite/gas/aarch64/udf-invalid.l: New.
        * testsuite/gas/aarch64/udf-invalid.d: New.

include * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_UNDEFINED.

opcodes * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
        * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
          (operand_general_constraint_met_p): validate AARCH64_OPND_UNDEFINED.
        * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry for
          FLD_imm16_2.
        * aarch64-asm-2.c: Regenerated.
        * aarch64-dis-2.c: Regenerated.
        * aarch64-opc-2.c: Regenerated.

1 files changed, 27 insertions, 26 deletions

diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index f94621f..ddb4e53 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -89,6 +89,7 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM10", OPD_F_SHIFT_BY_4 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immr}, "a 10-bit unsigned multiple of 16"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "BIT_NUM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_b5, FLD_b40}, "the bit number to be tested"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "EXCEPTION", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "UNDEFINED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_2}, "a 16-bit unsigned immediate"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit unsigned immediate"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit signed immediate"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "NZCV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_nzcv}, "a flag bit specifier giving an alternative value for each flag"},
@@ -241,48 +242,48 @@ const struct aarch64_operand aarch64_operands[] =
 static const unsigned op_enum_table [] =
 {
   0,
-  888,
   889,
   890,
-  893,
+  891,
   894,
   895,
   896,
   897,
-  891,
-  892,
   898,
+  892,
+  893,
   899,
-  921,
+  900,
   922,
   923,
-  926,
+  924,
   927,
   928,
   929,
   930,
-  924,
-  925,
   931,
+  925,
+  926,
   932,
-  986,
+  933,
   987,
   988,
   989,
+  990,
   12,
   636,
   637,
-  1181,
-  1183,
-  1185,
-  993,
-  1184,
   1182,
+  1184,
+  1186,
+  994,
+  1185,
+  1183,
   318,
   624,
   635,
   634,
-  991,
+  992,
   631,
   628,
   620,
@@ -292,34 +293,34 @@ static const unsigned op_enum_table [] =
   630,
   632,
   633,
-  1001,
+  1002,
   664,
   667,
   670,
   665,
   668,
-  824,
+  825,
   178,
   179,
   180,
   181,
   516,
-  758,
+  759,
   389,
   391,
   413,
   415,
-  1261,
-  1266,
-  1259,
-  1258,
   1262,
-  1269,
-  1271,
+  1267,
+  1260,
+  1259,
+  1263,
+  1270,
   1272,
-  1268,
-  1274,
   1273,
+  1269,
+  1275,
+  1274,
   131,
 };