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| author | Sudakshina Das <sudi.das@arm.com> | 2019-05-01 17:14:01 +0100 |
|---|---|---|
| committer | Sudakshina Das <sudi.das@arm.com> | 2019-05-01 17:14:01 +0100 |
| commit | b83b4b138298d2a6bfab11f533d7e315c0a1c97b (patch) | |
| tree | 78aa7ea03472fb0ee62aec2e1bcb7b5297ff42d6 /opcodes/aarch64-opc-2.c | |
| parent | 2ecde2b63245d4794a4967f318772e7166feb310 (diff) | |
| download | gdb-b83b4b138298d2a6bfab11f533d7e315c0a1c97b.zip gdb-b83b4b138298d2a6bfab11f533d7e315c0a1c97b.tar.gz gdb-b83b4b138298d2a6bfab11f533d7e315c0a1c97b.tar.bz2 | |
[BINUTILS, AArch64] Enable Transactional Memory Extension
This patch enables the new Transactional Memory Extension added recently
as part of Arm's new architecture technologies.
We introduce a new optional extension "tme" to enable this. The following
instructions are part of the extension:
* tstart <Xt>
* ttest <Xt>
* tcommit
* tcancel #<imm>
The ISA for the above can be found here:
https://developer.arm.com/docs/ddi0602/latest/base-instructions-alphabetic-order
*** gas/ChangeLog ***
2019-05-01 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add case for
AARCH64_OPND_TME_UIMM16.
(aarch64_features): Add "tme".
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/tme-invalid.d: New test.
* testsuite/gas/aarch64/tme-invalid.l: New test.
* testsuite/gas/aarch64/tme-invalid.s: New test.
* testsuite/gas/aarch64/tme.d: New test.
* testsuite/gas/aarch64/tme.s: New test.
*** include/ChangeLog ***
2019-05-01 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_TME): New.
(enum aarch64_opnd): Add AARCH64_OPND_TME_UIMM16.
*** opcodes/ChangeLog ***
2019-05-01 Sudakshina Das <sudi.das@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Add case for
AARCH64_OPND_TME_UIMM16.
(aarch64_print_operand): Likewise.
* aarch64-tbl.h (QL_IMM_NIL): New.
(TME): New.
(_TME_INSN): New.
(struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
Diffstat (limited to 'opcodes/aarch64-opc-2.c')
| -rw-r--r-- | opcodes/aarch64-opc-2.c | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 6902136..96eedd7 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -223,6 +223,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SVE_REG, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "an SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate for TME tcancel"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"}, {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"}, }; @@ -301,17 +302,17 @@ static const unsigned op_enum_table [] = 391, 413, 415, - 1254, - 1259, - 1252, - 1251, + 1258, + 1263, + 1256, 1255, - 1262, - 1264, - 1265, - 1261, - 1267, + 1259, 1266, + 1268, + 1269, + 1265, + 1271, + 1270, 131, }; |