aboutsummaryrefslogtreecommitdiff
path: root/opcodes/aarch64-opc-2.c
diff options
context:
space:
mode:
authorMatthew Malcomson <matthew.malcomson@arm.com>2019-05-09 10:29:18 +0100
committerMatthew Malcomson <matthew.malcomson@arm.com>2019-05-09 10:29:18 +0100
commitc469c86473273e115b267a6f8c93c8942deb93c4 (patch)
tree287fc69d0de95ceb865fef1bb99c4e1bd85b7ef8 /opcodes/aarch64-opc-2.c
parent116adc27470ed3682b6236e44e3b18838673036c (diff)
downloadgdb-c469c86473273e115b267a6f8c93c8942deb93c4.zip
gdb-c469c86473273e115b267a6f8c93c8942deb93c4.tar.gz
gdb-c469c86473273e115b267a6f8c93c8942deb93c4.tar.bz2
[binutils][aarch64] New SVE_ADDR_ZX operand.
Add AARCH64_OPND_SVE_ADDR_ZX operand that allows a vector of addresses in a Zn register, offset by an Xm register. This is used with scatter/gather SVE2 instructions. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (REG_ZR): Macro specifying zero register. (parse_address_main): Account for new addressing mode [Zn.S, Xm]. (parse_operands): Handle new SVE_ADDR_ZX operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_ADDR_ZX. (aarch64_print_operand): Add printing for SVE_ADDR_ZX. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
Diffstat (limited to 'opcodes/aarch64-opc-2.c')
-rw-r--r--opcodes/aarch64-opc-2.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 1a2aeff..eef857e 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -151,6 +151,7 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL1", (1 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL2", (2 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL3", (3 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn,FLD_Rm}, "vector of address with a scalar register offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"},