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| author | Jan Beulich <jbeulich@novell.com> | 2015-06-01 09:51:28 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2015-06-01 09:51:28 +0200 |
| commit | 3a8547d2fb5319890dda877fb313822053083c3a (patch) | |
| tree | 8c715e8520fd5e5f0cfb29e8596a4afb2b821e8e /opcodes/aarch64-gen.c | |
| parent | 015c54d5a6a052f074fab168bc70296131276e80 (diff) | |
| download | gdb-3a8547d2fb5319890dda877fb313822053083c3a.zip gdb-3a8547d2fb5319890dda877fb313822053083c3a.tar.gz gdb-3a8547d2fb5319890dda877fb313822053083c3a.tar.bz2 | |
x86/Intel: disassemble vcvt{,u}si2s{d,s} with correct operand order
As pointed out before, the documentation mandates the rounding mode to
follow the GPR, so disassembler should produce output accordingly.
gas/testsuite/
2015-06-01 Jan Beulich <jbeulich@suse.com>
* gas/i386/avx512f.s: Adjust operand order for Intel syntax
vcvt{,u}si2ss.
* gas/i386/x86-64-avx512f.s: Adjust operand order for Intel
syntax vcvt{,u}si2s{d,s}.
opcodes/
2015-06-01 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (print_insn): Swap rounding mode specifier and
general purpose register in Intel mode.
Diffstat (limited to 'opcodes/aarch64-gen.c')
0 files changed, 0 insertions, 0 deletions