aarch64: [SME] Add MOV and MOVA instructions

This patch is adding new MOV (alias) and MOVA SME instruction.

gas/ChangeLog:

	* config/tc-aarch64.c (enum sme_hv_slice): new enum.
	(struct reloc_entry): Added ZAH and ZAV registers.
	(parse_sme_immediate): Immediate parser.
	(parse_sme_za_hv_tiles_operand): ZA tile parser.
	(parse_sme_za_hv_tiles_operand_index): Index parser.
	(parse_operands): Added ZA tile parser calls.
	(REGNUMS): New macro. Regs with suffix.
	(REGSET16S): New macro. 16 regs with suffix.
	* testsuite/gas/aarch64/sme-2-illegal.d: New test.
	* testsuite/gas/aarch64/sme-2-illegal.l: New test.
	* testsuite/gas/aarch64/sme-2-illegal.s: New test.
	* testsuite/gas/aarch64/sme-2.d: New test.
	* testsuite/gas/aarch64/sme-2.s: New test.
	* testsuite/gas/aarch64/sme-2a.d: New test.
	* testsuite/gas/aarch64/sme-2a.s: New test.
	* testsuite/gas/aarch64/sme-3-illegal.d: New test.
	* testsuite/gas/aarch64/sme-3-illegal.l: New test.
	* testsuite/gas/aarch64/sme-3-illegal.s: New test.
	* testsuite/gas/aarch64/sme-3.d: New test.
	* testsuite/gas/aarch64/sme-3.s: New test.
	* testsuite/gas/aarch64/sme-3a.d: New test.
	* testsuite/gas/aarch64/sme-3a.s: New test.

include/ChangeLog:

	* opcode/aarch64.h (enum aarch64_opnd): New enums
	AARCH64_OPND_SME_ZA_HV_idx_src and
	AARCH64_OPND_SME_ZA_HV_idx_dest.
	(struct aarch64_opnd_info): New ZA tile vector struct.

opcodes/ChangeLog:

	* aarch64-asm.c (aarch64_ins_sme_za_hv_tiles):
	New inserter.
	* aarch64-asm.h (AARCH64_DECL_OPD_INSERTER):
	New inserter ins_sme_za_hv_tiles.
	* aarch64-dis.c (aarch64_ext_sme_za_hv_tiles):
	New extractor.
	* aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR):
	New extractor ext_sme_za_hv_tiles.
	* aarch64-opc.c (aarch64_print_operand):
	Handle SME_ZA_HV_idx_src and SME_ZA_HV_idx_dest.
	* aarch64-opc.h (enum aarch64_field_kind): New enums
	FLD_SME_size_10, FLD_SME_Q, FLD_SME_V and FLD_SME_Rv.
	(struct aarch64_operand): Increase fields size to 5.
	* aarch64-tbl.h (OP_SME_BHSDQ_PM_BHSDQ): New qualifiers
	aarch64-asm-2.c: Regenerate.
	aarch64-dis-2.c: Regenerate.
	aarch64-opc-2.c: Regenerate.

1 files changed, 58 insertions, 0 deletions

diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index cbc9051..94d3f8c 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -1748,6 +1748,64 @@ aarch64_ext_sve_float_zero_one (const aarch64_operand *self,
   return true;
 }
 
+/* Decode ZA tile vector, vector indicator, vector selector, qualifier and
+   immediate on numerous SME instruction fields such as MOVA.  */
+bool
+aarch64_ext_sme_za_hv_tiles (const aarch64_operand *self,
+                             aarch64_opnd_info *info, aarch64_insn code,
+                             const aarch64_inst *inst ATTRIBUTE_UNUSED,
+                             aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+  int fld_size = extract_field (self->fields[0], code, 0);
+  int fld_q = extract_field (self->fields[1], code, 0);
+  int fld_v = extract_field (self->fields[2], code, 0);
+  int fld_rv = extract_field (self->fields[3], code, 0);
+  int fld_zan_imm = extract_field (self->fields[4], code, 0);
+
+  /* Deduce qualifier encoded in size and Q fields.  */
+  if (fld_size == 0)
+    info->qualifier = AARCH64_OPND_QLF_S_B;
+  else if (fld_size == 1)
+    info->qualifier = AARCH64_OPND_QLF_S_H;
+  else if (fld_size == 2)
+    info->qualifier = AARCH64_OPND_QLF_S_S;
+  else if (fld_size == 3 && fld_q == 0)
+    info->qualifier = AARCH64_OPND_QLF_S_D;
+  else if (fld_size == 3 && fld_q == 1)
+    info->qualifier = AARCH64_OPND_QLF_S_Q;
+
+  info->za_tile_vector.index.regno = fld_rv + 12;
+  info->za_tile_vector.v = fld_v;
+
+  switch (info->qualifier)
+    {
+    case AARCH64_OPND_QLF_S_B:
+      info->za_tile_vector.regno = 0;
+      info->za_tile_vector.index.imm = fld_zan_imm;
+      break;
+    case AARCH64_OPND_QLF_S_H:
+      info->za_tile_vector.regno = fld_zan_imm >> 3;
+      info->za_tile_vector.index.imm = fld_zan_imm & 0x07;
+      break;
+    case AARCH64_OPND_QLF_S_S:
+      info->za_tile_vector.regno = fld_zan_imm >> 2;
+      info->za_tile_vector.index.imm = fld_zan_imm & 0x03;
+      break;
+    case AARCH64_OPND_QLF_S_D:
+      info->za_tile_vector.regno = fld_zan_imm >> 1;
+      info->za_tile_vector.index.imm = fld_zan_imm & 0x01;
+      break;
+    case AARCH64_OPND_QLF_S_Q:
+      info->za_tile_vector.regno = fld_zan_imm;
+      info->za_tile_vector.index.imm = 0;
+      break;
+    default:
+      assert (0);
+    }
+
+  return true;
+}
+
 /* Decode Zn[MM], where MM has a 7-bit triangular encoding.  The fields
    array specifies which field to use for Zn.  MM is encoded in the
    concatenation of imm5 and SVE_tszh, with imm5 being the less