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| author | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:26 +0100 |
|---|---|---|
| committer | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:26 +0100 |
| commit | fd1dc4a0c1b87c1efa7e0398fd47fd1e87fa0fb4 (patch) | |
| tree | 9f6e78bfe276c4fa1ebf89e523aab0df8217c7d1 /opcodes/aarch64-dis.c | |
| parent | 31e36ab341498bb477a46a0475100ec5d471c4f2 (diff) | |
| download | gdb-fd1dc4a0c1b87c1efa7e0398fd47fd1e87fa0fb4.zip gdb-fd1dc4a0c1b87c1efa7e0398fd47fd1e87fa0fb4.tar.gz gdb-fd1dc4a0c1b87c1efa7e0398fd47fd1e87fa0fb4.tar.bz2 | |
[binutils][aarch64] New sve_size_tsz_bhs iclass.
Add sve_size_tsz_bhs iclass needed for sqxtnb and similar instructions.
This iclass encodes one of three variants by the most significant bit
set in a 3-bit value where only one bit may be set.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_tsz_bhs
iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_size_tsz_bhs iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_size_tsz_bhs iclass decode.
Diffstat (limited to 'opcodes/aarch64-dis.c')
| -rw-r--r-- | opcodes/aarch64-dis.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index b42e4d5..6b53a2c 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -2843,6 +2843,17 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst) } break; + case sve_size_tsz_bhs: + i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19); + while (i != 1) + { + if (i & 1) + return FALSE; + i >>= 1; + variant += 1; + } + break; + case sve_shift_tsz_hsd: i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19); if (i == 0) |