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| author | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2016-11-18 10:02:16 +0000 |
|---|---|---|
| committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2016-11-18 10:02:16 +0000 |
| commit | c2c4ff8d52a2cd3263a547b0384692498714aa1b (patch) | |
| tree | 2b85adf0b7eb999a0272cad8dde99c54118c3945 /opcodes/aarch64-dis.c | |
| parent | 28617675c264213180a599bb4327bf162029636a (diff) | |
| download | gdb-c2c4ff8d52a2cd3263a547b0384692498714aa1b.zip gdb-c2c4ff8d52a2cd3263a547b0384692498714aa1b.tar.gz gdb-c2c4ff8d52a2cd3263a547b0384692498714aa1b.tar.bz2 | |
[AArch64] Add ARMv8.3 FCMLA and FCADD instructions
Add support for FCMLA and FCADD complex arithmetic SIMD instructions.
FCMLA has an indexed element variant where the index range has to be
treated specially because a complex number takes two elements and the
indexed vector size depends on the other operands.
These complex number SIMD instructions are part of ARMv8.3
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions
include/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1,
AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3.
(enum aarch64_op): Add OP_FCMLA_ELEM.
opcodes/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
(aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
(aarch64_opcode_table): Add fcmla and fcadd.
(AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
* aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
* aarch64-asm.c (aarch64_ins_imm_rotate): Define.
* aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
* aarch64-dis.c (aarch64_ext_imm_rotate): Define.
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
* aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
(operand_general_constraint_met_p): Rotate and index range check.
(aarch64_print_operand): Handle rotate operand.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
gas/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_IMM_ROT*.
* testsuite/gas/aarch64/advsimd-armv8_3.d: New.
* testsuite/gas/aarch64/advsimd-armv8_3.s: New.
* testsuite/gas/aarch64/illegal-fcmla.s: New.
* testsuite/gas/aarch64/illegal-fcmla.l: New.
* testsuite/gas/aarch64/illegal-fcmla.d: New.
Diffstat (limited to 'opcodes/aarch64-dis.c')
| -rw-r--r-- | opcodes/aarch64-dis.c | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 17bd342..bcf5232 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -351,6 +351,14 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, default: return 0; } + + if (inst->opcode->op == OP_FCMLA_ELEM) + { + /* Complex operand takes two elements. */ + if (info->reglane.index & 1) + return 0; + info->reglane.index /= 2; + } } return 1; @@ -703,6 +711,40 @@ aarch64_ext_fpimm (const aarch64_operand *self, aarch64_opnd_info *info, return 1; } +/* Decode rotate immediate for FCMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #rotate. */ +int +aarch64_ext_imm_rotate (const aarch64_operand *self, aarch64_opnd_info *info, + const aarch64_insn code, + const aarch64_inst *inst ATTRIBUTE_UNUSED) +{ + uint64_t rot = extract_field (self->fields[0], code, 0); + + switch (info->type) + { + case AARCH64_OPND_IMM_ROT1: + case AARCH64_OPND_IMM_ROT2: + /* rot value + 0 0 + 1 90 + 2 180 + 3 270 */ + assert (rot < 4U); + break; + case AARCH64_OPND_IMM_ROT3: + /* rot value + 0 90 + 1 270 */ + assert (rot < 2U); + rot = 2 * rot + 1; + break; + default: + assert (0); + return 0; + } + info->imm.value = rot * 90; + return 1; +} + /* Decode scale for e.g. SCVTF <Dd>, <Wn>, #<fbits>. */ int aarch64_ext_fbits (const aarch64_operand *self ATTRIBUTE_UNUSED, |