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| author | Richard Sandiford <richard.sandiford@arm.com> | 2016-09-21 16:51:24 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2016-09-21 16:51:24 +0100 |
| commit | aa2aa4c69429444836821a92cb99396d02dcb996 (patch) | |
| tree | e211f663adf01e52284b1654dd4de7d22fe5a3ed /opcodes/aarch64-dis.c | |
| parent | b5464a6825e40e6d8ab2dd86c7ff5d65bedd64d4 (diff) | |
| download | gdb-aa2aa4c69429444836821a92cb99396d02dcb996.zip gdb-aa2aa4c69429444836821a92cb99396d02dcb996.tar.gz gdb-aa2aa4c69429444836821a92cb99396d02dcb996.tar.bz2 | |
[AArch64][SVE 16/32] Use specific insert/extract methods for fpimm
FPIMM used the normal "imm" insert/extract methods, with a specific
test for FPIMM in the extract method. SVE needs to use the same
extractors, so rather than add extra checks for specific operand types,
it seemed cleaner to use a separate insert/extract method.
opcodes/
* aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
for FPIMM.
* aarch64-asm.h (ins_fpimm): New inserter.
* aarch64-asm.c (aarch64_ins_fpimm): New function.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_fpimm): New extractor.
* aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
(aarch64_ext_fpimm): New function.
* aarch64-dis-2.c: Regenerate.
Diffstat (limited to 'opcodes/aarch64-dis.c')
| -rw-r--r-- | opcodes/aarch64-dis.c | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 67daa66..4c3b521 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -598,9 +598,6 @@ aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info, imm = extract_all_fields (self, code); - if (info->type == AARCH64_OPND_FPIMM) - info->imm.is_fp = 1; - if (operand_need_sign_extension (self)) imm = sign_extend (imm, get_operand_fields_width (self) - 1); @@ -695,6 +692,17 @@ aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, return 1; } +/* Decode an 8-bit floating-point immediate. */ +int +aarch64_ext_fpimm (const aarch64_operand *self, aarch64_opnd_info *info, + const aarch64_insn code, + const aarch64_inst *inst ATTRIBUTE_UNUSED) +{ + info->imm.value = extract_all_fields (self, code); + info->imm.is_fp = 1; + return 1; +} + /* Decode scale for e.g. SCVTF <Dd>, <Wn>, #<fbits>. */ int aarch64_ext_fbits (const aarch64_operand *self ATTRIBUTE_UNUSED, |