aarch64: Add base support for Armv8-R

This patch adds the basic infrastructure needed to support Armv8-R in
AArch64 binutils: new command-line flags, new feature bits, a new BFD
architecture, and support for differentiating between architecture
variants in the disassembler.

The new command-line options added by this patch are -march=armv8-r in
GAS and -m aarch64:armv8-r in objdump.

The disassembler support is necessary since Armv8-R AArch64 introduces a
system register (VSCTLR_EL2) which shares an encoding with a different
system register (TTBR0_EL2) in Armv8-A. This also allows us to use the
correct preferred disassembly for the new DFB alias introduced in
Armv8-R.

bfd/ChangeLog:

2020-09-08  Alex Coplan  <alex.coplan@arm.com>

	* archures.c (bfd_mach_aarch64_8R): New.
	* bfd-in2.h: Regenerate.
	* cpu-aarch64.c (bfd_aarch64_arch_v8_r): New.
	(bfd_aarch64_arch_ilp32): Update tail pointer.

gas/ChangeLog:

2020-09-08  Alex Coplan  <alex.coplan@arm.com>

	* config/tc-aarch64.c (aarch64_archs): Add armv8-r.
	* doc/c-aarch64.texi: Document -march=armv8-r.

include/ChangeLog:

2020-09-08  Alex Coplan  <alex.coplan@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_V8_A): New.
	(AARCH64_FEATURE_V8_R): New.
	(AARCH64_ARCH_V8): Include new A-profile feature bit.
	(AARCH64_ARCH_V8_R): New.

opcodes/ChangeLog:

2020-09-08  Alex Coplan  <alex.coplan@arm.com>

	* aarch64-dis.c (arch_variant): New.
	(determine_disassembling_preference): Disassemble according to
	arch variant.
	(select_aarch64_variant): New.
	(print_insn_aarch64): Set feature set.

1 files changed, 33 insertions, 0 deletions

diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 326fabb..9d23b31 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -35,6 +35,7 @@ enum map_type
   MAP_DATA
 };
 
+static aarch64_feature_set arch_variant; /* See select_aarch64_variant.  */
 static enum map_type last_type;
 static int last_mapping_sym = -1;
 static bfd_vma last_stop_offset = 0;
@@ -2690,6 +2691,13 @@ determine_disassembling_preference (struct aarch64_inst *inst,
 	  DEBUG_TRACE ("skip %s as base opcode not match", alias->name);
 	  continue;
 	}
+
+      if (!AARCH64_CPU_HAS_FEATURE (arch_variant, *alias->avariant))
+	{
+	  DEBUG_TRACE ("skip %s: we're missing features", alias->name);
+	  continue;
+	}
+
       /* No need to do any complicated transformation on operands, if the alias
 	 opcode does not have any operand.  */
       if (aarch64_num_of_operands (alias) == 0 && alias->opcode == inst->value)
@@ -3360,6 +3368,24 @@ get_sym_code_type (struct disassemble_info *info, int n,
   return FALSE;
 }
 
+/* Set the feature bits in arch_variant in order to get the correct disassembly
+   for the chosen architecture variant.
+
+   Currently we only restrict disassembly for Armv8-R and otherwise enable all
+   non-R-profile features.  */
+static void
+select_aarch64_variant (unsigned mach)
+{
+  switch (mach)
+    {
+    case bfd_mach_aarch64_8R:
+      arch_variant = AARCH64_ARCH_V8_R;
+      break;
+    default:
+      arch_variant = AARCH64_ANY & ~(AARCH64_FEATURE_V8_R);
+    }
+}
+
 /* Entry-point of the AArch64 disassembler.  */
 
 int
@@ -3374,6 +3400,7 @@ print_insn_aarch64 (bfd_vma pc,
   unsigned int	size = 4;
   unsigned long	data;
   aarch64_operand_error errors;
+  static bfd_boolean set_features;
 
   if (info->disassembler_options)
     {
@@ -3385,6 +3412,12 @@ print_insn_aarch64 (bfd_vma pc,
       info->disassembler_options = NULL;
     }
 
+  if (!set_features)
+    {
+      select_aarch64_variant (info->mach);
+      set_features = TRUE;
+    }
+
   /* Aarch64 instructions are always little-endian */
   info->endian_code = BFD_ENDIAN_LITTLE;