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| author | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-07-01 15:17:22 +0100 |
|---|---|---|
| committer | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-07-01 15:17:22 +0100 |
| commit | 41be57caf36943d71ccc6ea70be27a4939399118 (patch) | |
| tree | 5c7137a796014a9b952ed9c622b7bad5815b2dce /opcodes/aarch64-dis.c | |
| parent | 65392b3edd1f6873204a4890efc286c8970abf4e (diff) | |
| download | gdb-41be57caf36943d71ccc6ea70be27a4939399118.zip gdb-41be57caf36943d71ccc6ea70be27a4939399118.tar.gz gdb-41be57caf36943d71ccc6ea70be27a4939399118.tar.bz2 | |
[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AES
I had mistakenly given all variants of the new SVE2 instructions
pmull{t,b} a dependency on the feature +sve2-aes.
Only the variant specifying .Q -> .D sizes should have that
restriction.
This patch fixes that mistake and updates the testsuite to have extra
tests (matching the given set of tests per line in aarch64-tbl.h that
the rest of the SVE2 tests follow).
We also add a line in the documentation of the command line to clarify
how to enable `pmull{t,b}` of this larger size. This is needed because
all other instructions gated under the `sve2-aes` architecture extension
are marked in the instruction documentation by an `HaveSVE2AES` check
while pmull{t,b} is gated under the `HaveSVE2PMULL128` check.
Regtested targeting aarch64-linux.
gas/ChangeLog:
2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
* testsuite/gas/aarch64/illegal-sve2-aes.d: Update tests.
* testsuite/gas/aarch64/illegal-sve2.l: Update tests.
* doc/c-aarch64.texi: Add special note of pmull{t,b}
instructions under the sve2-aes architecture extension.
* testsuite/gas/aarch64/illegal-sve2.s: Add small size
pmull{t,b} instructions.
* testsuite/gas/aarch64/sve2.d: Add small size pmull{t,b}
disassembly.
* testsuite/gas/aarch64/sve2.s: Add small size pmull{t,b}
instructions.
include/ChangeLog:
2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): sve_size_013
renamed to sve_size_13.
opcodes/ChangeLog:
2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
sve_size_13 icode to account for variant behaviour of
pmull{t,b}.
* aarch64-dis-2.c: Regenerate.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
sve_size_13 icode to account for variant behaviour of
pmull{t,b}.
* aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
(OP_SVE_VVV_Q_D): Add new qualifier.
(OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
(struct aarch64_opcode): Split pmull{t,b} into those requiring
AES and those not.
Diffstat (limited to 'opcodes/aarch64-dis.c')
| -rw-r--r-- | opcodes/aarch64-dis.c | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 6b53a2c..7ae844a 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -2822,14 +2822,11 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst) variant = i - 1; break; - case sve_size_013: - i = extract_field (FLD_size, inst->value, 0); - if (i == 2) - return FALSE; - if (i == 3) - variant = 2; - else - variant = i; + case sve_size_13: + /* Ignore low bit of this field since that is set in the opcode for + instructions of this iclass. */ + i = (extract_field (FLD_size, inst->value, 0) & 2); + variant = (i >> 1); break; case sve_shift_tsz_bhsd: |