[AArch64][SVE 28/32] Add SVE FP immediate operands

This patch adds support for the new SVE floating-point immediate
operands.  One operand uses the same 8-bit encoding as base AArch64,
but in a different position.  The others use a single bit to select
between two values.

One of the single-bit operands is a choice between 0 and 1, where 0
is not a valid 8-bit encoding.  I think the cleanest way of handling
these single-bit immediates is therefore to use the IEEE float encoding
itself as the immediate value and select between the two possible values
when encoding and decoding.

As described in the covering note for the patch that added F_STRICT,
we get better error messages by accepting unsuffixed vector registers
and leaving the qualifier matching code to report an error.  This means
that we carry on parsing the other operands, and so can try to parse FP
immediates for invalid instructions like:

	fcpy	z0, #2.5

In this case there is no suffix to tell us whether the immediate should
be treated as single or double precision.  Again, we get better error
messages by picking one (arbitrary) immediate size and reporting an error
for the missing suffix later.

include/
	* opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd.
	(AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO)
	(AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise.

opcodes/
	* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
	immediate operands.
	* aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
	* aarch64-opc.c (fields): Add corresponding entry.
	(operand_general_constraint_met_p): Handle the new SVE FP immediate
	operands.
	(aarch64_print_operand): Likewise.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
	(ins_sve_float_zero_one): New inserters.
	* aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
	(aarch64_ins_sve_float_half_two): Likewise.
	(aarch64_ins_sve_float_zero_one): Likewise.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
	(ext_sve_float_zero_one): New extractors.
	* aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
	(aarch64_ext_sve_float_half_two): Likewise.
	(aarch64_ext_sve_float_zero_one): Likewise.
	* aarch64-dis-2.c: Regenerate.

gas/
	* config/tc-aarch64.c (double_precision_operand_p): New function.
	(parse_operands): Use it to calculate the dp_p input to
	parse_aarch64_imm_float.  Handle the new SVE FP immediate operands.

1 files changed, 32 insertions, 25 deletions

diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 4527456..110cf2e 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -10426,21 +10426,21 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 27:
     case 35:
     case 36:
-    case 135:
-    case 136:
-    case 137:
-    case 138:
     case 139:
     case 140:
     case 141:
     case 142:
-    case 155:
-    case 156:
-    case 157:
-    case 158:
+    case 143:
+    case 144:
+    case 145:
+    case 146:
     case 159:
     case 160:
+    case 161:
+    case 162:
     case 163:
+    case 164:
+    case 167:
       return aarch64_ext_regno (self, info, code, inst);
     case 8:
       return aarch64_ext_regrt_sysins (self, info, code, inst);
@@ -10483,16 +10483,16 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 69:
     case 70:
     case 71:
-    case 132:
-    case 134:
-    case 147:
-    case 148:
-    case 149:
-    case 150:
+    case 136:
+    case 138:
     case 151:
     case 152:
     case 153:
     case 154:
+    case 155:
+    case 156:
+    case 157:
+    case 158:
       return aarch64_ext_imm (self, info, code, inst);
     case 38:
     case 39:
@@ -10504,9 +10504,10 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 43:
       return aarch64_ext_shll_imm (self, info, code, inst);
     case 46:
+    case 129:
       return aarch64_ext_fpimm (self, info, code, inst);
     case 60:
-    case 130:
+    case 134:
       return aarch64_ext_limm (self, info, code, inst);
     case 61:
       return aarch64_ext_aimm (self, info, code, inst);
@@ -10597,22 +10598,28 @@ aarch64_extract_operand (const aarch64_operand *self,
       return aarch64_ext_sve_aimm (self, info, code, inst);
     case 128:
       return aarch64_ext_sve_asimm (self, info, code, inst);
-    case 129:
-      return aarch64_ext_inv_limm (self, info, code, inst);
+    case 130:
+      return aarch64_ext_sve_float_half_one (self, info, code, inst);
     case 131:
-      return aarch64_ext_sve_limm_mov (self, info, code, inst);
+      return aarch64_ext_sve_float_half_two (self, info, code, inst);
+    case 132:
+      return aarch64_ext_sve_float_zero_one (self, info, code, inst);
     case 133:
+      return aarch64_ext_inv_limm (self, info, code, inst);
+    case 135:
+      return aarch64_ext_sve_limm_mov (self, info, code, inst);
+    case 137:
       return aarch64_ext_sve_scale (self, info, code, inst);
-    case 143:
-    case 144:
+    case 147:
+    case 148:
       return aarch64_ext_sve_shlimm (self, info, code, inst);
-    case 145:
-    case 146:
+    case 149:
+    case 150:
       return aarch64_ext_sve_shrimm (self, info, code, inst);
-    case 161:
+    case 165:
       return aarch64_ext_sve_index (self, info, code, inst);
-    case 162:
-    case 164:
+    case 166:
+    case 168:
       return aarch64_ext_sve_reglist (self, info, code, inst);
     default: assert (0); abort ();
     }