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| author | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2016-11-18 09:49:06 +0000 |
|---|---|---|
| committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2016-11-18 09:49:06 +0000 |
| commit | 3f06e55061d0d8f72dfd11f6c432c23f45d9b597 (patch) | |
| tree | 6f63bbc6a1be5e476b4333ef45e16516cc272869 /opcodes/aarch64-asm.c | |
| parent | 6ec49e7c0aeb6d98e379319b565aee2c89388615 (diff) | |
| download | gdb-3f06e55061d0d8f72dfd11f6c432c23f45d9b597.zip gdb-3f06e55061d0d8f72dfd11f6c432c23f45d9b597.tar.gz gdb-3f06e55061d0d8f72dfd11f6c432c23f45d9b597.tar.bz2 | |
[AArch64] Add ARMv8.3 combined pointer authentication load instructions
Add support for ARMv8.3 LDRAA and LDRAB combined pointer authentication and
load instructions.
These instructions authenticate the base register and load 8 byte from it plus
a scaled 10-bit offset with optional writeback to update the base register.
A new instruction class (ldst_imm10) and operand type (AARCH64_OPND_ADDR_SIMM10)
were introduced to handle the special addressing form.
include/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10.
(enum aarch64_insn_class): Add ldst_imm10.
opcodes/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (QL_X1NIL): New.
(arch64_opcode_table): Add ldraa, ldrab.
(AARCH64_OPERANDS): Add "ADDR_SIMM10".
* aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
* aarch64-asm.c (aarch64_ins_addr_simm10): Define.
* aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
* aarch64-dis.c (aarch64_ext_addr_simm10): Define.
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
* aarch64-opc.c (fields): Add data for FLD_S_simm10.
(operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
(aarch64_print_operand): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
gas/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_ADDR_SIMM10.
(fix_insn): Likewise.
(warn_unpredictable_ldst): Handle ldst_imm10.
* testsuite/gas/aarch64/pac.s: Add ldraa and ldrab tests.
* testsuite/gas/aarch64/pac.d: Likewise.
* testsuite/gas/aarch64/illegal-ldraa.s: New.
* testsuite/gas/aarch64/illegal-ldraa.l: New.
* testsuite/gas/aarch64/illegal-ldraa.d: New.
Diffstat (limited to 'opcodes/aarch64-asm.c')
| -rw-r--r-- | opcodes/aarch64-asm.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 34be794..64051a9 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -606,6 +606,30 @@ aarch64_ins_addr_simm (const aarch64_operand *self, return NULL; } +/* Encode the address operand for e.g. LDRAA <Xt>, [<Xn|SP>{, #<simm>}]. */ +const char * +aarch64_ins_addr_simm10 (const aarch64_operand *self, + const aarch64_opnd_info *info, + aarch64_insn *code, + const aarch64_inst *inst ATTRIBUTE_UNUSED) +{ + int imm; + + /* Rn */ + insert_field (self->fields[0], code, info->addr.base_regno, 0); + /* simm10 */ + imm = info->addr.offset.imm >> 3; + insert_field (self->fields[1], code, imm >> 9, 0); + insert_field (self->fields[2], code, imm, 0); + /* writeback */ + if (info->addr.writeback) + { + assert (info->addr.preind == 1 && info->addr.postind == 0); + insert_field (self->fields[3], code, 1, 0); + } + return NULL; +} + /* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<pimm>}]. */ const char * aarch64_ins_addr_uimm12 (const aarch64_operand *self, |