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| author | Richard Sandiford <richard.sandiford@arm.com> | 2016-09-21 16:51:09 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2016-09-21 16:51:09 +0100 |
| commit | 42408347b86745fdbd4bec9ee3a6a3fee31c4dee (patch) | |
| tree | 5134e249ebca1ba93871174da6773e65965ae96d /opcodes/aarch64-asm.c | |
| parent | 4989adac848eb8f2fee8b98d9615d2fded22623b (diff) | |
| download | gdb-42408347b86745fdbd4bec9ee3a6a3fee31c4dee.zip gdb-42408347b86745fdbd4bec9ee3a6a3fee31c4dee.tar.gz gdb-42408347b86745fdbd4bec9ee3a6a3fee31c4dee.tar.bz2 | |
[AArch64][SVE 14/32] Make aarch64_logical_immediate_p take an element size
SVE supports logical immediate operations on 8-bit, 16-bit and 32-bit
elements, treating them as aliases of operations on 64-bit elements in
which the immediate is replicated. This patch therefore replaces the
"32-bit/64-bit" input to aarch64_logical_immediate_p with a more
general "number of bytes" input.
opcodes/
* aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
with an esize parameter.
(operand_general_constraint_met_p): Update accordingly.
Fix misindented code.
* aarch64-asm.c (aarch64_ins_limm): Update call to
aarch64_logical_immediate_p.
Diffstat (limited to 'opcodes/aarch64-asm.c')
| -rw-r--r-- | opcodes/aarch64-asm.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 2430be5..8fbd66f 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -436,11 +436,11 @@ aarch64_ins_limm (const aarch64_operand *self, const aarch64_opnd_info *info, { aarch64_insn value; uint64_t imm = info->imm.value; - int is32 = aarch64_get_qualifier_esize (inst->operands[0].qualifier) == 4; + int esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier); if (inst->opcode->op == OP_BIC) imm = ~imm; - if (aarch64_logical_immediate_p (imm, is32, &value) == FALSE) + if (aarch64_logical_immediate_p (imm, esize, &value) == FALSE) /* The constraint check should have guaranteed this wouldn't happen. */ assert (0); |