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| author | Yury Khrustalev <yury.khrustalev@arm.com> | 2024-02-21 12:52:23 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2024-03-18 16:54:06 +0000 |
| commit | 4792a423d264cfb6dbb656ea97b1c84d1b4e55b6 (patch) | |
| tree | b9ed74a4a37b8e8881e533325a9fa8777949532c /opcodes/aarch64-asm.c | |
| parent | ee0fa6627079ebd16843d9d3fb4e24a5af545ded (diff) | |
| download | gdb-4792a423d264cfb6dbb656ea97b1c84d1b4e55b6.zip gdb-4792a423d264cfb6dbb656ea97b1c84d1b4e55b6.tar.gz gdb-4792a423d264cfb6dbb656ea97b1c84d1b4e55b6.tar.bz2 | |
aarch64: Add support for (M)ADDPT and (M)SUBPT instructions
The following instructions are added in this patch:
- ADDPT and SUBPT - Add/Subtract checked pointer
- MADDPT and MSUBPT - Multiply Add/Subtract checked pointer
These instructions are part of Checked Pointer Arithmetic extension.
This patch adds assembler and disassembler support for these instructions
with relevant checks. Tests are included as well.
A new flag "+cpa" added to documentation. This flag enables CPA extension.
Regression tested on the aarch64-none-linux-gnu target and no regressions
have been found.
Diffstat (limited to 'opcodes/aarch64-asm.c')
| -rw-r--r-- | opcodes/aarch64-asm.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 29e96e2..5a55ca2 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1020,6 +1020,21 @@ aarch64_ins_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED, return true; } +/* Encode the LSL-shifted register operand for e.g. + ADDPT <Xd|SP>, <Xn|SP>, <Xm>{, LSL #<amount>}. */ +bool +aarch64_ins_reg_lsl_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED, + const aarch64_opnd_info *info, aarch64_insn *code, + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) +{ + /* Rm */ + insert_field (FLD_Rm, code, info->reg.regno, 0); + /* imm3 */ + insert_field (FLD_imm3_10, code, info->shifter.amount, 0); + return true; +} + /* Encode an SVE address [<base>, #<simm4>*<factor>, MUL VL], where <simm4> is a 4-bit signed value and where <factor> is 1 plus SELF's operand-dependent value. fields[0] specifies the field that |