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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-01-15 09:37:32 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2024-01-15 11:45:41 +0000 |
| commit | 39092c7a1fb0927fbbdb40e1142de816d6f3f097 (patch) | |
| tree | 39c066e97256ea52262332db3601294caf5708b6 /opcodes/aarch64-asm.c | |
| parent | 88601c2d941b004b443dc4bfdf3b93ea1983d136 (diff) | |
| download | gdb-39092c7a1fb0927fbbdb40e1142de816d6f3f097.zip gdb-39092c7a1fb0927fbbdb40e1142de816d6f3f097.tar.gz gdb-39092c7a1fb0927fbbdb40e1142de816d6f3f097.tar.bz2 | |
aarch64: Add SVE2.1 dupq, eorqv and extq instructions.
Hi,
This patch add support for SVE2.1 instruction dupq, eorqv and extq.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Diffstat (limited to 'opcodes/aarch64-asm.c')
| -rw-r--r-- | opcodes/aarch64-asm.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 1dfd59d..0de09f0 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1220,6 +1220,21 @@ aarch64_ins_sve_index (const aarch64_operand *self, return true; } +/* Encode Zn.<T>[<imm>], where <imm> is an immediate with range of 0 to one less + than the number of elements in 128 bit, which can encode il:tsz. */ +bool +aarch64_ins_sve_index_imm (const aarch64_operand *self, + const aarch64_opnd_info *info, aarch64_insn *code, + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) +{ + insert_field (self->fields[0], code, info->reglane.regno, 0); + unsigned int esize = aarch64_get_qualifier_esize (info->qualifier); + insert_fields (code, (info->reglane.index * 2 + 1) * esize, 0, + 2, self->fields[1],self->fields[2]); + return true; +} + /* Encode a logical/bitmask immediate for the MOV alias of SVE DUPM. */ bool aarch64_ins_sve_limm_mov (const aarch64_operand *self, @@ -2079,6 +2094,7 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst) case sme_shift: case sve_index: + case sve_index1: case sve_shift_pred: case sve_shift_unpred: case sve_shift_tsz_hsd: |