[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.

Include a new iclass to extract the variant from the most significant 3
bits of this operand.

Instructions such as rshrnb include a constant shift amount as an
operand, where the most significant three bits of this operand determine
what size elements the instruction is operating on.

The new SVE_SHRIMM_UNPRED_22 operand denotes this constant encoded in
bits 22:20-19:18-16 while the new sve_shift_tsz_hsd iclass denotes that
the SVE qualifier is encoded in bits 22:20-19.

gas/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22
	operand.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22
	operand.
	(enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
	* aarch64-asm.c (aarch64_ins_sve_shrimm):
	(aarch64_encode_variant_using_iclass): Handle
	sve_shift_tsz_hsd iclass encode.
	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
	sve_shift_tsz_hsd iclass decode.
	* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
	for SVE_SHRIMM_UNPRED_22.
	(aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
	* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
	operand.

1 files changed, 11 insertions, 10 deletions

diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index ac5bda4..00ab9b3 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -638,7 +638,6 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 169:
     case 170:
     case 171:
-    case 184:
     case 185:
     case 186:
     case 187:
@@ -647,8 +646,9 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 190:
     case 191:
     case 192:
-    case 197:
-    case 200:
+    case 193:
+    case 198:
+    case 201:
       return aarch64_ins_regno (self, info, code, inst, errors);
     case 14:
       return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -660,7 +660,7 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 32:
     case 33:
     case 34:
-    case 203:
+    case 204:
       return aarch64_ins_reglane (self, info, code, inst, errors);
     case 35:
       return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -696,7 +696,6 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 82:
     case 159:
     case 161:
-    case 176:
     case 177:
     case 178:
     case 179:
@@ -704,7 +703,8 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 181:
     case 182:
     case 183:
-    case 202:
+    case 184:
+    case 203:
       return aarch64_ins_imm (self, info, code, inst, errors);
     case 43:
     case 44:
@@ -845,16 +845,17 @@ aarch64_insert_operand (const aarch64_operand *self,
       return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
     case 174:
     case 175:
+    case 176:
       return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
-    case 193:
     case 194:
     case 195:
     case 196:
+    case 197:
       return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
-    case 198:
-      return aarch64_ins_sve_index (self, info, code, inst, errors);
     case 199:
-    case 201:
+      return aarch64_ins_sve_index (self, info, code, inst, errors);
+    case 200:
+    case 202:
       return aarch64_ins_sve_reglist (self, info, code, inst, errors);
     default: assert (0); abort ();
     }