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| author | Jan Beulich <jbeulich@suse.com> | 2020-01-30 11:36:33 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2020-01-30 11:36:33 +0100 |
| commit | aeab2b26dbea33221db4debaf31c97277cfaea5e (patch) | |
| tree | ea035fa04bc87aab42f5381626f3a213273fc992 /opcodes/ChangeLog | |
| parent | 873494c89fb44747c7514687da25fc163c791b84 (diff) | |
| download | gdb-aeab2b26dbea33221db4debaf31c97277cfaea5e.zip gdb-aeab2b26dbea33221db4debaf31c97277cfaea5e.tar.gz gdb-aeab2b26dbea33221db4debaf31c97277cfaea5e.tar.bz2 | |
x86-64: honor vendor specifics for near RET
While vendors agree about default operand size (64 bits) and hence
unavilability of a 32-bit form, AMD honors a 16-bit operand size
override (0x66) while Intel doesn't.
Diffstat (limited to 'opcodes/ChangeLog')
| -rw-r--r-- | opcodes/ChangeLog | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 3748121..19c2772 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,14 @@ 2020-01-30 Jan Beulich <jbeulich@suse.com> + * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators. + (dis386): Use them to replace C2/C3 table entries. + (x86_64_table): Add X86_64_C2 and X86_64_C3 entries. + * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64 + ones. Use Size64 instead of DefaultSize on Intel64 ones. + * i386-tbl.h: Re-generate. + +2020-01-30 Jan Beulich <jbeulich@suse.com> + * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword forms. (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop |