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| author | Jan Beulich <jbeulich@novell.com> | 2018-11-06 11:43:55 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2018-11-06 11:43:55 +0100 |
| commit | b50c9f31661be05bcd73fb1158e02f606e696948 (patch) | |
| tree | 80c3662241c3d1bc92b3e45c5e86dbf081bb6e2d /opcodes/ChangeLog | |
| parent | 931d03b75aa934abc10a70f1aa3ca1192f32ed3d (diff) | |
| download | gdb-b50c9f31661be05bcd73fb1158e02f606e696948.zip gdb-b50c9f31661be05bcd73fb1158e02f606e696948.tar.gz gdb-b50c9f31661be05bcd73fb1158e02f606e696948.tar.bz2 | |
x86: adjust {,E}VEX.W handling for PEXTR* / PINSR*
PEXTR{B,W} and PINSR{B,W}, just like for AVX512BW, are WIG, no matter
that the SDM uses a nonstandard description of that fact.
PEXTRD, even with EVEX.W set, ignores that bit outside of 64-bit mode,
just like its AVX counterpart.
Diffstat (limited to 'opcodes/ChangeLog')
| -rw-r--r-- | opcodes/ChangeLog | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 8b88018..9f82b3f 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,20 @@ 2018-11-06 Jan Beulich <jbeulich@suse.com> + * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2, + VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2, + EVEX_W_0F3A22_P_2): Delete. + (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w} + entries up one level in the hierarchy. + (OP_E_memory): Handle dq_mode when determining Disp8 shift + value. + * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q} + entries up one level in the hierarchy. + * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to + VexWIG for AVX flavors. + * i386-tbl.h: Re-generate. + +2018-11-06 Jan Beulich <jbeulich@suse.com> + * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri, vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd, vcvtusi2ss, kmovd): Drop VexW=1. |