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| author | Jan Beulich <jbeulich@novell.com> | 2018-11-06 11:42:54 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2018-11-06 11:42:54 +0100 |
| commit | 931d03b75aa934abc10a70f1aa3ca1192f32ed3d (patch) | |
| tree | 9c539669d1a6a693f3fbd5293224151329b63c0f /opcodes/ChangeLog | |
| parent | fd71a3756e2dd1eae116d77dc5ec58391c4840d8 (diff) | |
| download | gdb-931d03b75aa934abc10a70f1aa3ca1192f32ed3d.zip gdb-931d03b75aa934abc10a70f1aa3ca1192f32ed3d.tar.gz gdb-931d03b75aa934abc10a70f1aa3ca1192f32ed3d.tar.bz2 | |
x86: adjust {,E}VEX.W handling outside of 64-bit mode
Many VEX-/EVEX-encoded instructions accessing GPRs become WIG outside of
64-bit mode. The respective templates should specify neither VexWIG nor
VexW0, but instead the setting of the bit should be determined from
- REX.W in 64-bit mode,
- the setting established through -mvexwig= / -mevexwig= otherwise.
This implies that the evex-wig2 testcase needs to go away, as being
wrong altogether.
A few test additions desirable here will only happen in later patches,
as the disassembler needs adjustments first.
Once again SSE2AVX templates are left alone, for it being unclear what
the behavior there should be.
Diffstat (limited to 'opcodes/ChangeLog')
| -rw-r--r-- | opcodes/ChangeLog | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 444ab05..8b88018 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,12 @@ 2018-11-06 Jan Beulich <jbeulich@suse.com> + * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri, + vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd, + vcvtusi2ss, kmovd): Drop VexW=1. + * i386-tbl.h: Re-generate. + +2018-11-06 Jan Beulich <jbeulich@suse.com> + * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256, EVex512, EVexLIG, EVexDYN): New. (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM |